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Technical Reports (183)

    2023
  1. Fumiaki Onishi, Ryosei Otaka, Kazuki Fujita, Tomoki Suetsugu, Tohma Kawasumi, Toshiaki Kitamura, Hironori Kasahara, Keiji Kimura, "Investigation of code generation techniques for vector multicore targeting using the deep learning compiler TVM", IPSJ SIG Technical Report, Vol.2023-ARC-254, No.8, pp.1-8, Aug. 2023.
    2. 2022
  2. Raito HAYASHI, Hiroki MIKAMI, Akira NODOMI, Sadahiro KIMURA, Keiji KIMURA, Hironori KASAHARA, "Preliminary Evaluation of Low Power Optimized ORB-SLAM3 on Jetson Xavier NX", IEICE Technical Report, CPSY2022-40, Mar. 2023.
  3. Ryosei OTAKA, Honoka KOIKE, Ryusei ISONO, Toma KAWASUMI, Toshiaki KITAMURA, Hiroki MIKAMI, Akira NODOMI, Sadahiro KIMURA, Keiji KIMURA, Hironori KASAHARA, "Evaluation of Convolution Layers on an Embedded Vector Multticore having Local Memory Architecture", IPSJ SIG Technical Report, Vol.2023-EMB-62, No.32, Mar. 2023.
    4. 2021
  4. Kazuki YAMAMOTO, Takugo OSAKABE, Honoka KOIKE, Tohma KAWASUMI, Kazuki FUJITA, Toshiaki KITAMURA, Akihiro KAWASHIMA, Akira NODOMI, Sadahiro KIMURA, Keiji KIMURA, Hironori KASAHARA, "LocalMapping Parallelization and CPU Allocation Method on ORB-SLAM3", IEICE Technical Report, Vol.121, No.425, CPSY2021-58, pp.79-84, Mar. 2022.
  5. Yuta TSUMURA, Tohma KAWASUMI, Hiroki MIKAMI, Daiki KAWAKAMI, Takero HOSOMI, Shingo OIDATE, Keiji KIMURA, Hironori KASAHARA, "Parallelism Analysis of Ladder Programs by OSCAR Automatic Parallelizing Compiler", IPSJ SIG Technical Report, Vol.2022-EMB-59, No.53, Mar. 2022.
    6. 2020
  6. Yuta Tadokoro, Keiji Kimura, Hironori Kasahara, "Parallelization and Vectorization of SpMM for Sparse Neural Network", Information Processing Society of Japan, Special Interest Group on System Architecture (ARC236@ETNET2021), Mar. 2021.
  7. Ryo Koyama, Yuta Tsumura, Toma Kawasumi, Yuya Nakada, Dan Umeda, Keiji Kimura, Hironori Kasahara, "Automatic Parallelization of MATLAB/Simulink Applications Using OSCAR Compiler", Information Processing Society of Japan, Special Interest Group on System Architecture (ARC236@ETNET2021), Mar. 2021.
    8. 2019
  8. Toma Kawasumi, Tilman Priesner, Masato Noguchi, Jixin Han, Hiroki Mikami, Takahiro Miyajima, Keishiro Tanaka, Keiji Kimura, Hironori Kasahara, "Extensions of OSCAR Compiler for Parallelizing C++ Programs", Information Processing Society of Japan, Special Interest Group on System Architecture (ARC232@ETNET2020), Feb. 2020.
  9. Yuta Tadokoro, Hiroki Mikami, Takeo Hosomi, Keiji Kimura, Hironori Kasahara, "Automatic Vector-Parallelization by Collaboration of Oscar Automatic Parallelizing Compiler and NEC Vectorizing Compiler", Information Processing Society of Japan, Special Interest Group on System Architecture (ARC232@ETNET2020), Feb. 2020.
  10. Kazuki Yamamoto, Kazuki Fujita, Tomoya Kashimata, Ken Takahashi, Boma A. Adhi, Toshiaki Kitamura, Akihiro Kawashima, Akira Nodomi, Yuji Mori, Keiji Kimura, Hironori Kasahara, "Consideration of Accelerator Cost Estimation Method in Multi-Target Automatic Parallelizing Compiler", Information Processing Society of Japan, Special Interest Group on System Architecture (ARC232@ETNET2020), Feb. 2020.
  11. Keiji Kimura, Kazuki Fujita, Kazuki Yamamoto, Tomoya Kashimata,Toshiaki Kitamura, Hironori Kasahara, "Automatically Parallelizing Compiler Cooperative OSCAR Vector Multicore", International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems , Feb. 2020.
    12. 2018
  12. Tomoya Kashimata, Toshiaki Kitamura, Keiji Kimura, Hironori Kasahara, "Speedup of indirect load by DMA cascading", Information Processing Society of Japan(2018-ARC-234), Jan. 2019.
    13. 2017
  13. Ken Takahashi, Satoshi Karino,Kazuki Miyamoto , Takumi Kawata , Tomoya Kashimata,Tetsuya Makita,Toshiaki Kitamura, Keiji Kimura, HironoriKasahara, "Development of Compilation Flow and Evaluation of OSCAR Vector Multicore Architecture", The 80th National Conversion of Information Processing Society of Japan, Mar. 2018.
  14. Tomoya Kashimata, Satoshi Karino, Kazuki Miyamoto, Takumi Kawata, Ken Takahashi, Tetsuya Makita, Toshiaki Kitamura, Keiji Kimura, Hironori Kasahara, "FPGA implementation of OSCAR Vector Accelerator", The 80th National Conversion of Information Processing Society of Japan, Mar. 2018.
  15. Kazuki Miyamoto, Tetsuya Makita, Ken Takahashi, Tomoya Kashimata, Takumi Kawada, Satoshi Karino, Toshiaki Kitamura, Keiji Kimura, Hironori Kasahara, "Automatic parallelizing and vectorizing compiler framework for OSCAR vector multicore processor", Information Processing Society of Japan, Special Interest Group onSystem Architecture (ARC222@ETNET2018), Mar. 2018.
  16. Tomoya Shirakawa, Yuto abe, Yoshitake Ooki, Akimasa Yoshida, Keiji Kimura, Hironori Kasahara, "Automatic Local Memory Management Using Hierarchical Adjustable Block for Multicores and Its Performance Evaluation", Technical Report of IPSJ, 2017-ARC-220 (DesignGaia2017), Nov. 2017.
    17. 2016
  17. Rina Fujino, Jixin Han, Mamoru Shimaoka, Hiroki Mikami, Takahiro Miyajima, Moriyuki Takamura, Keiji Kimura, Hironori Kasahara, "Code Generating Method with Profile Feedback for Reducing Compilation Time of Automatic Parallelizing Compiler", Information Processing Society of Japan, Special Interest Group onSystem Architecture (ARC217@ETNET2017), Mar. 2017.
  18. Jin Miyata,Mamoru Shimaoka, Hiroki Mikami, Hirofumi Nishi, Hitoshi Suzuki, Keiji Kimura, Hironori Kasahara, "Parallel Processing of Automobile Real-time Control on Multicore System with Multiple Clusters", Information Processing Society of Japan, Special Interest Group onSystem Architecture (ARC217@ETNET2017), Mar. 2017.
  19. Tatsuya Onoguchi, Ayane Hayashi, Katsuyuki Utaka, Yuichi Matsushima,Keiji Kimura, Hironori Kasahara, "Hierarchical Interconnection Network Extension for Gen 5 Simulator Considering Large Scale Systems", Information Processing Society of Japan, Special Interest Group onSystem Architecture (ARC217@ETNET2017), Mar. 2017.
  20. Akira Maruoka, Yuya Mushu, Satoshi Karino, Takashi Mochiyama, Toshiaki Kitamura, Sachio Kamiya, Moriyuki Takamura,Keiji Kimura, Hironori Kasahara, "A Compilation Framework for Multicores having Vector Accelerators using LLVM", Summer United Workshops on Parallel, Distributed and Cooperative Processing, Technical Report of IPSJ,Vol.2016-ARC-221 No.4, Aug. 2016.
    21. 2015
  21. Naoto Kageura, Tamami Wake, Ji Xin Han, Keiji Kimura, Hironori Kasahara, "The parallelism abstraction method with a data conversion at analysis in a OSCAR compiler", Technical Report of IPSJ, 2016-HPC-153, Mar. 2016.
  22. Tomoyuki Shibasaki, Kohei Kuwajima, Mariko Okumura, Hiroki Mikami, Keiji Kimura, Kohei Kadoshita, Keiichi Nakano, Hironori Kasahara, "Automatic Multigrain Parallel Processing for 3D Noise Reduction Using OSCAR Compiler", Technical Report of IPSJ, 2016-HPC-153, Mar. 2016.
  23. Mariko Okumura, Tomoyuki Shibasaki, Kohei Kuwajima, Hiroki Mikami, Keiji Kimura, Kohei Kadoshita, Keiichi Nakano, Hironori Kasahara, "Multigrain Parallelization of Program for Medical Image Filtering", Technical Report of IPSJ, 2016-HPC-153, Mar. 2016.
  24. Kohei Yamamoto, Tomoya Shirakawa, Akimasa Yoshida, Keiji Kimura, Hironori Kasahara, "Multicore Local Memory Management Scheme using Data Multidimensional Aligned Decomposition", Information Processing Society of Japan, Special Interest Group on Embedded Systems (SIGEMB), Vol.2016-ARC-218, No.10, Vol.2016-SLDM174, No.10, Jan. 2016.
    25. 2014
  25. Daichi Fukui, Mamoru Shimaoka, Hiroki Mikami, Dominic Hillenbrand, Keiji Kimura, Hironori Kasahara, "Tracing method of a parallelized program using Linux ftrace on a multicore processor", Summer United Workshops on Parallel, Distributed and Cooperative Processing, Technical Report of IPSJ, Vol.2014-ARC-211 No.6, Jul. 2014.
  26. Shuhei Iizuka, Hideo Yamamoto, Tomohiro Hirano,Youhei Kishimoto, Takashi Goto, Hiroki Mikami, Keiji Kimura, Hironori Kasahara, "Power Reduction of Real-time Dynamic Image Processing on Haswell Multicore Using OSCAR Compiler", Information Processing Society of Japan, Special Interest Group on Embedded Systems(SIGEMB), Mar. 2015.
  27. Takashi Goto, Kohei Muto, Tomohiro Hirano, Hiroki Mikami , Uichiro Takahashi(Fujitsu), Sakae Inoue(Fujitsu), Keiji Kimura, Hironori Kasahara, "Dynamic Scheduling Algorithm for Automatically Parallelized and Power Reduced Applications on Multicore Systems", Information Processing Society of Japan, Special Interest Group on Embedded Systems(SIGEMB), Mar. 2015.
  28. Tamami Wake, Shuhei Iizuka, Hiroki Mikami, Keiji Kimura, Hironori Kasahara, "Evaluation of Parallelization of video decoding on Intel and ARM Multicore", Information Processing Society of Japan, Special Interest Group on Embedded Systems(SIGEMB), Mar. 2015.
  29. Yohei Kishimoto, Masayoshi Mase, Keiji Kimura, Hironori Kasahara, "Evaluation of Software Cashe Coherency Cotrol Scheme by an Automatic Parallelizing Compiler", IPSJ SIG Technical Report Vol.2014-ARC-213No.19, Dec. 2014.
  30. Bui Duc Binh, Tomohiro Hirano, Hiroki Mikami, Dominic Hillenbrand, Keiji Kimura, Hironori Kasahara, "Android Demonstration System of Automatic Parallelization and Power Optimization by OSCAR Compiler ", Summer United Workshops on Parallel, Distributed and Cooperative Processing, Technical Report of IPSJ, Vol.2014-ARC-211 No.6, Jul. 2014.
    31. 2013
  31. Gakuho Taguchi, Keiji Kimura, Hironori Kasahara, "A Parallelizing Compiler Cooperative Acceleration Technique of Multicore Architecture Simulation using a Statistical Method", IPSJ SIG Technical Report, Mar. 2014.
  32. Shohei Yamada, Keiji Kimura, Hironori Kasahara, "A Latency Reduction Technique for IDS by Allocating Decomposed Signature on Multi-core", IPSJ SIG Technical Report Vol.2013-ARC-201, Mar. 2014.
  33. Yuuki Furuyama, Hiroki Mikami, Keiji Kimura, Hironori Kasahara, "Automatic Parallelization of Small Point FFT on Multicore Processor", IPSJ SIG Technical Report Vol.2013-ARC-201, Mar. 2014.
  34. Takashi Goto, Kohei Muto, Hideo Yamamoto, Tomohiro Hirano, Hiroki Mikami, Keiji Kimura, Hironori Kasahara, "Profile-Based Automatic Parallelization for Android 2D Rendering by Using OSCAR Compiler", Technical Report ofIPSJ, Vol.2013-ARC-207 No.12, Dec. 2013.
  35. Tomohiro Hirano, Hideo Yamamoto, Kohei Muto, Hiroki Mikami, Takashi Goto, Dominic Hillenbrand, Keiji Kimura, Hironori Kasahara, "Automatic Power Control on Multicore Android Devices", Summer United Workshops on Parallel, Distributed and Cooperative Processing, Technical Report ofIPSJ,Vol.2013-ARC-206 No.23, Aug. 2013.
  36. Akihiro Kawashima, Yohei Kanehagi, Akihiro Hayashi, Keiji Kimura, Hironori Kasahara, "An Evaluation of Hardware Barrier Synchronization Mechanism Considering Hierarchical Processor Grouping using OSCAR API Standard Translator", Summer United Workshops on Parallel, Distributed and Cooperative Processing, Technical Report ofIPSJ,Vol.2013-ARC-206 No.16, Aug. 2013.
  37. Yasir I. M. Al-Dosary, Yuki Furuyama, Dominic Hillenbrand, Keiji Kimura, Hironori Kasahara, Seinosuke Narita, "Enhancing the Performance of a Multiplayer Game by Using a Parallelizing Compiler", Technical Report ofIPSJ, Apr. 2013.
    38. 2012
  38. Hideo Yamamoto, Takashi Goto, Tomohiro Hirano, Kouhei Muto, Hiroki Mikami, Dominic Hillenbrand, Akihiro Hayashi, Keiji Kimura, Hironori Kasahara, "An Investigation of Parallelization and Evaluation on Commercial Multi-core Smart Device", Technical Report of IPSJ, Vol. 2013-OS-124 No. 000310, Feb. 2013.
  39. Gakuho Taguchi, Yoichi Abe, Keiji Kimura, Hironori Kasahara, "A Parallelizing Compiler Cooperative Multicore Architecture Simulator with Changeover Mechanism of Simulation Modes", Technical Report of IPSJ, Vol.2012-ARC-203 N0.14, Jan. 2013.
  40. Yoichi Abe, Gakuho Taguchi, Keiji Kimura, Hironori Kasahara, "An Acceleration Technique of Many-core Architecture Simulation with Parallelized Applications by Statistical Technique", Technical Report of IPSJ, Vol.2012-ARC-203 N0.13, Jan. 2013.
  41. Youhei Kanehagi, Dan Umeda, Hiroki Mikami, Akihiro Hayashi, Mitsuo Sawada(TOYOTA), Keiji Kimura, Hironori Kasahara, "Parallelization of Automobile Engine Control Software on Multicore Processor", Technical Report of IPSJ, Vol.2013-ARC-203 No.2, Jan. 2013.
  42. Dominic Hillenbrand, Yuuki Furuyama, Akihiro Hayashi, Hiroki Mikami, Keiji Kimura, Hironori Kasahara, "Opportunities and Challenges of Application-Power Control in the Age of Dark Silicon", Technical Report of IPSJ, Vol.2012-ARC-202HPC137 No.26, Dec. 2012.
  43. Mamoru Shimaoka, Hiroki Mikami, Akihiro Hayashi, Yasutaka Wada, Keiji Kimura, Hidekazu Morita (HITACHI), Kunio Uchiyama (HITACHI), Hironori Kasahara, "Automatic Parallelization of Ground Motion Simulator", Technical Report of IPSJ, Vol.2012-ARC-202HPC137 No.11, Dec. 2012.
  44. Cecilia Gonzalez-Alvarez, Youhei Kanehagi, Kosei Takemoto, Yohei Kishimoto, Kohei Muto, Hiroki Mikami, Akihiro Hayashi, Keiji Kimura, Hironori Kasahara, "Automatic parallelization with OSCAR API Analyzer: a cross-platform performance evaluation", Technical Report of IPSJ, Vol.2012-ARC-202HPC137 No.10, Dec. 2012.
  45. Yuuki Furuyama, Mamoru Shimaoka, Hiroki Mikami, Akihiro Hayashi, Keiji Kimura, Hironori Kasahara, "Realization of 1 Watt Web Service with RP-X Low-power Multicore Processor", Technical Report of IPSJ, Vol.2012-ARC-201 No.24, Aug. 2012.
  46. Dan Umeda, Youhei Kanehagi, Hiroki Mikami, Akihiro Hayashi, Mituhiro Tani, Yuji Mori, Keiji Kimura, Hironori Kasahara, "Parallelization of Basic Engine Controll Software Model on Multicore Processor", Technical Report of IPSJ, Vol.2012-ARC-201 No.22, Aug. 2012.
    47. 2011
  47. Yoichi Abe, Ryo Ishizuka, Ryota Daigo, Gakuho Taguchi, Keiji Kimura, Hironori Kasahara, "An Examination of Accelerating Many-core Architecture Simulation for Parallelized Media Applications", Technical Report of IPSJ, Vol. 2012-ARC-199, No. 3, Mar. 2012.
  48. Keiichi Tabata, Keiji Kimura, Hironori Kasahara, "Inlining Analysis of Exception Flow and Fast Method Dispatch on Automatic Parallelization of Java", Technical Report of IPSJ, Vol. 2012-ARC-199, No. 9, Mar. 2012.
  49. Keiji Kimura, Masayoshi Mase, Hironori Kasahara, "A Definition of Parallelizable C by JISX0180:2011 "Framework of establishing coding guidelines for embedded system development"", ETNET2012, Mar. 2012.
  50. Akihiro Hayashi, Takuji Matsumoto, Hiroki Mikami, Keiji Kimura, Keiji Yamamoto, Hironori Saki, Yasuyuki Takatani and Hironori Kasahara, "Automatic Parallelization of Dose Calculation Engine for A Particle Therapy on SMP Servers", Technical Report of IPSJ, Vol.2011-ARC189HPC132-2, Nov. 2011.
  51. Ryo Ishizuka, Youichi Abe, Ryota Daigo, Keiji Kimura and Hironori Kasahara, "An Evaluation of An Acceleration Technique of Many Core Architectre Simulatior Considering Science Technology Calculation Program Structure", Technical Report of IPSJ, Vol.2011-HPC-130-16, July.2011.
  52. Yuki Taira, Keiji Kimura and Hironori Kasahara, "Examination of Parallelization by CUDA in SPEC benchmark program", Technical Report of IPSJ, Vol.2011-HPC-130-16, Jul.2011.
  53. Akihiro Hayashi, Takeshi Sekiguchi, Masayoshi Mase, Yasutaka Wada, Keiji Kimura and Hironori Kasahara, "Hiding I/O overheads with Parallelizing Compiler for Media Applications", Techinical Report of IPSJ, Vol.2011-ARC-195OS117-14, Apr. 2011.
    54. 2010
  54. Hiroki Mikami, Shumpei Kitaki, Takafumi Sato, Masayoshi Mase, Keiji Kimura, Kazuhisa Ishizaka, Junji Sakai, Masato Edahiro, Hironori Kasahara, "Evaluation of Power Consumption by Executing Media Applications on Low-power Multicore RP2", Technical Report of IPSJ, 2011-ARC-194-1, Mar. 2011.
  55. Takuya Sato, Hiroki Mikami, Akihiro Hayashi, Masayoshi Mase, Keiji Kimura, Hironori Kasahara, "Evaluation of Parallelizable C Programs by the OSCAR API Standard Translator", Technical Report of IPSJ, 2010-ARC-191-2, Oct. 2010.
  56. Akihiro Hayashi, Yasutaka Wada, Takeshi Watanabe, Takeshi Sekiguchi, Masahiro Mase, Keiji Kimura, Masayuki Ito, Jun Hasegawa, Makoto Sato, Tohru Nojiri, Kunio Uchiyama, Hironori Kasahara, "A Compiler Framework for Heterogeneous Multicores for Consumer Electronics", Technical Report of IPSJ, 2010-ARC-190-7(SWoPP2010), Aug. 2010.
  57. Yasutaka Wada, Akihiro Hayashi, Takeshi Watanabe, Takeshi Sekiguchi, Masahiro Mase, Jun Shirako, Keiji Kimura, Masayuki Ito, Jun Hasegawa, Makoto Sato, Tohru Nojiri, Kunio Uchiyama, Hironori Kasahara, "Performance of Power Reduction Scheme by a Compiler on Heterogeneous Multicore for Consumer Electronics "RP-X"", Technical Report of IPSJ, 2010-ARC-190-8(SWoPP2010), Aug. 2010.
  58. Ryo Ishizuka, Toshiya Ootomo, Ryouta Daigo, Keiji Kimura, Hironori Kasahara, "An Acceleration Technique of Many Core Architecture Simulator Considering Program Structure", Technical Report of IPSJ, 2010-ARC-190-20, Jul. 2010.
  59. Masayoshi Mase, Keiji Kimura, Hironori Kasahara, "Parallelizing Compiler Directed Software Coherence", Technical Report of IPSJ, 2010-ARC-189-7, Apr. 2010.
    60. 2009
  60. Takamichi Miyamoto,Masayoshi Mase, Keiji Kimura,Kazuhisa Ishizaka,Junji Sakai, Masato Edahiro, "Processing Performance of Automatically Parallelized Applications on Embedded Multicore with Running Multiple Applications", Technical Report of IPSJ, 2010-ARC-188 No.9, Mar. 2010.
  61. Hiroki Mikami,Takamichi Miyamoto, Keiji Kimura, Hironori Kasahara, "Hierarchical Parallel Processing of H.264/AVC Encoder on an Multicore Processeor", Technical Report of IPSJVol.2010-ARC-187 No.22 Vol.2010-EMB-15 No.22, Jan. 2010.
  62. Masayoshi Mase, Keiji Kimura, Hironori Kasahara,Yuta murata, "Masayoshi Mase, Yuta Murata, Keiji Kimura, Hironori Kasahara, "Element-Sensitive Pointer Analysis for Automatic Parallelization", IPSJ-SIGPRO, Oct. 2009.
  63. Masayoshi Mase, Keiji Kimura, Hironori Kasahara, "Automatic Parallelization of Parallelizable C Programs on Multicore Processors", Technical Report of IPSJ, 2009-ARC-184-15(SWoPP2009), Aug. 2009.
    64. 2008
  64. Mamoru Shimaoka, Kazuhiro Imaizumi, Fumiyo Takano, Keiji Kimura, Hironori Kasahara, "Performance Evaluation of Minimum Execution Time Multiprocessor Scheduling Algorithms Using Standard Task Graph Set Ver3 Consider Parallelism of Task Graphs and Deviation of Task Execution Time", Technical Report of IEICE, Feb. 2009.
  65. Teruo Kamiyama, Yasutaka Wada, Akihiro Hayashi, Masayoshi Mase, Hirofumi Nakano, Takeshi Watanabe, Keiji Kimura, Hironori Kasahara, "Performance Evaluation of Parallelizing Compiler Cooperated Heterogeneous Multicore Architecture Using Media Applications", THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS, TECHNICAL REPORT OF IEICE. (ICD2008/140), Jan. 2009.
  66. Taku Momozono, Hirofumi Nakano, Masayoshi Mase, Keiji Kimura, Hironori Kasahara, "Local Memory Management Scheme by a Compiler for Multicore Processor", THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS, TECHNICAL REPORT OF IEICE. (ICD2008/141), Jan. 2009.
  67. Ryo Nakagawa, Masayoshi Mase, Jun Shirako, Keiji Kimura, Hironori Kasahara, "A Power Saving Scheme on Multicore Processors Using OSCAR API", THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS, TECHNICAL REPORT OF IEICE. (ICD2008/145), Jan. 2009.
  68. Masayoshi Mase, Daisuke Baba, Harumi Nagayama, Yuta Murata, Keiji Kimura, Hironori Kasahara, "Automatic Parallelization of Restricted C Programs using Pointer Analysis", Technical Report of IPSJ, May. 2008.
  69. Kaito Yamada, Masayoshi Mase, Jun Shirako, Keiji Kimura, Masayuki Ito, Toshihiro Hattori, Hiroyuki Mizuno, Kunio Uchiyama, Hironori Kasahara, "An Evaluation of Barrier Synchronization Mechanism Considering Hierarchical Processor Grouping", Technical Report of IPSJ, May. 2008.
    70. 2007
  70. Takamichi Miyamoto, Kei Tamura, Hiroaki Tano, Hiroki Mikami, Saori Asaka, Masayoshi Mase, Keiji Kimura, Hironori Kasahara, "Parallelization for Multimedia Processing on Multicore Processors", Technical Report of IPSJ, 2007-ARC-175-05 (DesignGaia2007), Nov. 2007.
  71. Hiroaki Shikano, Masaki Ito, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Masafumi Onouchi, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, "Evaluation of Heterogeneous Multicore Architecture with AAC-LC Stereo Encoding", THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS, TECHNICAL REPORT OF IEICE. (ICD2007-71), Vol. 107, No. 195, pp.11-16, Aug. 2007.
  72. Yasutaka Wada, Akihiro Hayashi, Taketo Iyoku, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara, "A Hierarchical Coarse Grain Task Static Scheduling Scheme on a Heterogeneous Multicore", Technical Report of IPSJ, 2007-ARC-174-17(SWoPP2007), Aug. 2007.
  73. Akihiro Hayashi, Taketo Iyoku, Ryo Nakagawa, Shigeru Matsumoto, Kaito Yamada, Naoto Oshiyama, Jun Shirako, Yasutaka Wada, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara, "Compiler Control Power Saving for Heterogeneous Multicore Processor", Technical Report of IPSJ, 2007-ARC-174-18(SWoPP2007), Aug. 2007.
  74. Masayoshi Mase, Daisuke Baba, Harumi Nagayama, Hiroaki Tano, Takeshi Masuura, Takamichi Miyamoto, Jun Shirako, Hirofumi Nakano, Keiji Kimura, Tatsuya Kamei, Toshihiro Hattori, Atsushi Hasegawa, Makoto Sato, Masaki Ito, Toshihiko Odaka, Hironori Kasahara, "Mutligrain Parallel Processing in SMP Execution Mode on a Multicore for Consumer Electronics", Technical Report of IPSJ, 2007-ARC-173-05, May. 2007.
  75. Kiyoshi hayase, Yutaka Yoshida, Tatsuya Kamei, Shinichi Shibahara, Osamu Nishii, Toshihiro Hattori, Atsushi Hasegawa, Masashi Takada, Naohiko Irie, Kunio Uchiyama, Toshihiko Odaka, Kiwamu Takada, Keiji Kimura, Hironori Kasahara, "A 4320MIPS four Processor-core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption", Technical Report of IPSJ, 2007-ARC-173-06, May. 2007.
    76. 2006
  76. Tsuyoshi Miura, Tomohiro Tagawa, Yusuke Muramatsu, Akinori Ikemi, Masahiro Nakagawa, Hirofumi Nakano, Jun Shirako, Keiji Kimura, Hironori Kasahara, "A Local Memory Management Scheme in Multigrain Parallelizing Compiler", Technical Report of IPSJ, 2007-ARC-172/HPC-109-11, Mar. 2007.
  77. Takamichi Miyamoto, Saori Asaka, Nobuhito Kamakura, Hiromasa Yamauchi, Masayoshi Mase, Jun Shirako, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara, "Automatic Parallelization for Multimedia Applications on Multicore Processors", Technical Report of IPSJ, 2007-ARC-171-13, Jan. 2007.
  78. Jun Shirako, Tomohiro Tagawa, Tsuyoshi Miura, Takamichi Miyamoto, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara, "Performance of OSCAR Multigrain Parallelizing Compiler on SMP Servers and Embedded Multicore", Technical Report of IPSJ, 2006-ARC-170-02 (DesignGaia2006), Nov. 2006.
  79. Masayoshi Mase, Daisuke Baba, Harumi Nagayama, Hiroaki Tano, Takeshi Masuura,　Koji Fukatsu, Takamichi Miyamoto, Jun Shirako, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara, "Automatic Parallelization of Restricted C Progurams in OSCAR Compiler", Technical Report of IPSJ, 2006-ARC-170-01 (DesignGaia2006), Nov. 2006.
  80. Hirofumi Nakano, Takumi Nito, Takanori Maruyama, Masahiro Nakagawa, Yuki Suzuki, Yosuke Naito, Takamichi Miyamoto, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, "Local Memory Management on OSCAR Multicore", Technical Report of IPSJ, 2006-ARC-169-28 (SWoPP2006), Aug. 2006.
  81. Fumiyo Takano, Yoshitaka Maekawa, Hironori Kasahara, Seinosuke Narita, "Parallelization of Multi-Path Concurrent Search for Iterative Deepening using Proof and Disproof Numbers", Technical Report of IPSJ, 2006-HPC-103-17 (SWoPP2006), Aug. 2006.
    82. 2005
  82. Takamichi Miyamoto, Masahiro Nakagawa, Shoichiro Asano, Yosuke Naito, Takumi Nito, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara, "Data Transfer Overlap of Coarse Grain Task Parallel Processing on a Multicore Processor", Technical Report of IPSJ, 2006-ARC-167/HPC-105-10, Feb. 2006.
  83. Hironori Kasahara, "Parallelizing Compiler Cooperated Low Power High Effective Performance Multi-core Processors", Technical Report of IPSJ, 2006-ARC-166-6 (SHINING2006), Jan. 2006.
  84. Hiroaki Shikano, Yuki Suzuki, Yasutaka Wada, Jun Shirako, Keiji Kimura, Hironori Kasahara, "Preliminary Evaluation of Heterogeneous Chip Multi-Processor with MP3 Audio Encoder", Technical Report of IPSJ, 2006-ARC-166-1 (SHINING2006), Jan. 2006.
  85. Yasutaka Wada, Naoto Oshiyama, Yuki Suzuki, Yosuke Naito, Jun Shirako, Keiji Kimura, Hironori Kasahara, "A Static Scheduling Scheme for Coarse Grain Tasks on a Heterogeneous Chip Multi Processor", Technical Report of IPSJ, 2006-ARC-166-3 (SHINING2006), Jan. 2006.
  86. Hiforumi Nakano, Shoichiro Asano, Yosuke Naito, Takumi Nito, Tomohiro Tagawa, Takaumichi Miyamoto, Takeshi Kodaka, Keiji Kimura, Hironori Kasahara, "Data Localization on a Multicore Processor", Technical Report of IPSJ, 2005-ARC-165-10, pp.51-56, Dec. 2005.
  87. Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara, "Compiler Control Power Saving Scheme for Homogeneous Multiprocessor", Technical Report of IPSJ, 2005-ARC-164-10 (SwoPP2005), pp.55-60, Aug. 2005.
    88. 2004
  88. Yasutaka Wada, Jun Shirako, Kazuhisa Ishizaka, Keiji Kimura, Hironori Kasahara, "Evaluation of Multigrain Parallelism on OSCAR Chip Multi Processor", Technical Report of IPSJ, 2004-ARC-159-11, Jul. 2004.
  89. Hirofumi Nakano, Yosuke Naito, Takahisa Suzuki, Takeshi Kodaka, Kazuhisa Ishizaka, Keiji Kimura, Hironori Kasahara, "Data Localization using Data Transfer Unit on OSCAR Chip Multiprocessor", Technical Report of IPSJ, 2004-ARC-159-20, Jul. 2004.
  90. Takeshi Kodaka, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara, "Parallel Processing for MPEG2 Encoding on OSCAR Chip Multiprocessor", Technical Report of IPSJ, 2004-ARC-160-07, Dec. 2004.
  91. Akira Kuroda, Keiji Kimura, Hironori Kasahara, "Performance Evaluation of Electronic Circuit Simulation Using Code Generation Method without Array Indirect Access", Technical Report of IPSJ, ARC2005-161-1 (SHINING2005), Jan. 2005.
  92. Jun Shirako, Takamichi Miyamoto, Kazuhisa Ishizaka, Motoki Obata, Keiji Kimura, Hironori Kasahara, "Performance of OSCAR Multigrain Parallelizing Compiler on Shared Memory Multiprocessor Serers", Technical Report of IPSJ, ARC2004-161-5, Jan. 2005.
  93. Takanari Matsuzawa, Shinya Sakaida, Takao Tobita, Hironori Kasahara, "Performance Evaluation of Minimum Execution Time Multiprocessor Scheduling Algorithms using Standard Task Graph Set Which Takes into Account Parallelism of Task Graphs", Technical Report of IPSJ, ARC2004-161-9, Jan. 2005.
    94. 2003
  94. Kazuhisa Ishizaka, Motoki Obata, Hironori Kasahara, "Inter-Array Padding for Data Localization with Static Scheduling", Technical Report of IPSJ, 2003-ARC-153-11, May. 2003.
  95. Takeshi Kodaka, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara, "Parallel Processing on MPEG2 Encoding for OSCAR Chip Multiprocessor", Technical Report of IPSJ, 2003-ARC-154-10, Aug. 2003.
  96. Hirofumi Nakano, Takeshi Kodaka, Keiji Kimura, Hironori Kasahara, "Data Localization Scheme using Static Scheduling on Chip Multiprocessor", Technical Report of IPSJ, 2003-ARC-154-14, Aug. 2003.
  97. Takamichi Miyamoto, Takahiro Yamaguchi, Takao Tobita, Kazuhisa Ishizaka, Keiji Kimura, Hironori Kasahara, "The Data Prefetching of Coarse Grain Task Parallel Processing on Symmetric Multi Processor Machine", Technical Report of IPSJ, 2003-ARC-155-06, Nov. 2003.
  98. Takeshi Kodaka, Hirofumi Nakano, Keiji Kimura and Hironori Kasahara, "Parallel Processing for MPEG2 Encoding using Data Localization", Technical Report of IPSJ, 2004-ARC-156-3, Feb. 2004.
    99. 2002
  99. Yasutaka Wada, Hirofumi Nakano, Keiji Kimura, Motoki Obata, Hironori Kasahara, "Evaluation of Overhead with Coarse Grain Task Parallel Processing on SMP Machines", Technical Report of IPSJ, ARC2002-148-3, May. 2002.
  100. Jun Shirako, Hiroki Kaminaga, Noriaki Kondo, Kazuhisa Ishizaka, Motoki Obata, Hironori Kasahara, "Coarse Grain Task Parallel Processing with Automatic Determination Scheme of Parallel Processing Layer", Technical Report of IPSJ, ARC2002-148-4, May. 2002.
  101. Motoki Obata, Jun Shirako, Kazuhisa Ishizaka, Hironori Kasahara, "Performance of OSCAR Multigrain Parallelizing Compiler on SMPs", Technical Report of IPSJ, ARC2002-149-20(SWoPP2002), Aug. 2002.
  102. Kazuhisa Ishizaka, Hirofumi Nakano, Motoki Obata, Hironori Kasahara, "Cache Optimization among Coarse Grain Tasks considering Line Conflict Miss", Technical Report of IPSJ, ARC2002-149-25(SWoPP2002), Aug. 2002.
  103. Takeshi Kodaka, Takahisa Suzuki, Keiji Kimura, Hironori Kasahara, "Multigrain Parallel Processing on Motion Vector Estimation for Single Chip Multiprocessor", Technical Report of IPSJ, ARC2002-150-6, Nov. 2002.
  104. Keiji Kimura, Takeshi Kodaka, Motoki Obata, Hironori Kasahara, "Multigrain Parallel Processing on OSCAR Chip Multiprocessor", Technical Report of IPSJ, ARC2002-150-7, Nov. 2002.
  105. Jun Shirako, Kouhei Nagasawa, Kazuhisa Ishizaka, Motoki Obata, Hironori Kasahara, "Inline Expansion for Improvement of Multi Grain Parallelism", Technical Report of IPSJ, ARC2003-151-2??SHINING2003), Jan. 2003.
  106. Hirofumi Nakano, Takeshi Kodaka, Keiji Kimura, Hironori Kasahara, "Data Localization using Coarse Grain Task Parallelization on Chip Multiprocessor", Technical Report of IPSJ, ARC2003-151-3(SHINING2003), Jan. 2003.
    107. 2001
  107. Takeshi Kodaka, Naohisa Miyashita, Keiji Kimura, Hironori Kasahara, "Near Fine Grain Parallel Processing on Multimedia Application for Single Chip Multiprocessor", IPSJ SIG Notes 2001-ARC-144-11, Aug. 2001.
  108. Hirofumi Nakano, Kazuhisa Ishizaka, Motoki Obata, Hironori Kasahara, "A Static Scheduling Scheme for Coarse Grain Tasks considering Cache Optimization on SMP", IPSJ SIG Notes 2001-ARC-144-12, Aug. 2001.
  109. Takayuki Uchida, Takechi Kodaka, Keiji Kimura, Hironori Kasahara, "Multigrain Parallel Processing on Single Chip Multiprocessor", Technical Report of IPSJ, ARC2002-146-3, Feb. 2002.
  110. Takeshi Kodaka, Takayuki Uchida, Keiji Kimura, Hironori Kasahara, "Multigrain Parallel Processing for JPEG Encoding Program on an OSCAR type Single Chip Multiprocessor", Technical Report of IPSJ, ARC2002-146-4, Feb. 2002.
  111. Motoki Obata, Kazuhisa Ishizaka, Hiroki Kaminaga, Hirofumi Nakano, Akimasa Yoshida, Hironori Kasahara, "Coarse Grain Task Parallel Processing on Commercial SMPs", Technical Report of IPSJ, ARC2002-146-10, Feb. 2002.
  112. Shin-ya Kumazawa, Kazuhisa Ishizaka, Motoki Obata, Hironori Kasahara, "An Analysis-time Procedure Inlining and Flexible Cloning Scheme for Coarse-grain Automatic Parallelizing Compilation", Technical Report of IPSJ, ARC, Mar. 2002.
  113. Satoshi Yagi, Hiroki Itagaki, Hirofumi Nakano, Kazuhisa Ishizaka, Motoki Obata, Akimasa Yoshida, Hironori Kasahara, "A Macrotask selection technique for Data-Localization Scheme on Shared-memory Multi-Processor", Technical Report of IPSJ, ARC, Mar. 2002.
    114. 2000
  114. Kazuhisa Ishizaka, Motoki Obata, Hironori Kasahara, "Coarse Grain Task Parallel Processing with OpenMP API", Technical Report of IPSJ, ARC-139-32, Aug. 2000.
  115. Keiji Kimura, Takayuki Uhida, Takayuki Kato, Hironori Kasahara, "Processor Core Architecture of Single Chip Multiprocessor for Near Fine Grain Parallel Processing", Technical Report of IPSJ, ARC-139-16, Aug. 2000.
  116. Hiroshi Koide, Nobuhiro Yamagishi, Hiroshi Takemiya, Hironori Kasahara, "Evaluation of the resource information prediction in the resource information server", Technical Report of IPSJ,PRO, Aug. 2000.
  117. Kazuhisa Ishizaka, Satoshi Yagi, Motoki Obata, Akimasa Yoshida, Hironori Kasahara, "Evaluation of coarse grain task parallel processing on the shared memory multiprocessor system", Technical Report of IPSJ, ARC-141-7, Jan. 2001.
  118. Akimasa Yoshida, Satoshi Yagi, Hironori Kasahara, "A Data-Localization Scheme for Macrotask-Graph with Data Dependencies on SMP", Technical Report of IPSJ, ARC-141-6, Jan. 2001.
    119. 1999
  119. K. Kimura, K. Manaka, W. Ogata, M. Okamoto, H. Kasahara, "Performance Evaluation of Near Fine Grain Parallel Processing on the Single Chip Multiprocessor", Technical Report of IPSJ, ARC-134-5, pp.19-24, Aug. 1999.
  120. K. Iwai, M. Obata, K. Kimura, H. Amano, H. Kasahara, "Memory access analyzer for a Multi-grain parallel processing", Technical Report of IEICE,CPSY99, Vol. 99, No. 252, pp.1-8, Aug. 1999.
  121. A. Narikiyo, H. Matsuzaki, M. Obata, A. Yoshida, H. Kasahara, "A Data-Localization Scheme for Macrotask-Graphs with Data Dependencies", Technical Report of IPSJ, ARC-136-8, pp.43-48, Jan. 2000.
  122. K. Manaka, R. Osakabe, Y. Maekawa, H. Kasahara, "Performance Evaluation and Parallelize of Electronic Circuit Simulation which generate code without array indirect access", IPSJ ARC/HPC, Mar. 2000.
  123. K. Yoshii, G. Matsui, M. Obata, S. Kumazawa, H. Kasahara, "An Analysis-time Procedure Inlining Scheme for Multi-grain Automatic Parallelizing Compilation", IPSJ ARC/HPC, Mar. 2000.
    124. 1998
  124. H. Kasahara, W. Ogata, K. Kimura, M. Obata, T. Tobita, D. Inaishi, "A Multigrain Parallelizing Compiler and Its Architectural Support", THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS, TECHNICAL REPORT OF IEICE. (ICD98-10, CPSY98-10, FTS98-10), Apr. 1998.
  125. M. Obata, G. Matsui, H. Matsuzaki, K. Kimura, D. Inaishi, Y. Ujigawa, T. Yamamoto, M. Okamoto, H. Kasahara, "Evaluation of Multigrain Parallelism using OSCAR FORTRAN Compiler", Technical Report of IPSJ, ARC-130-3, Aug. 1998.
  126. K. Kimura, W. Ogata, M. Okamoto, H. Kasahara, "Multigrain parallel Processing on the Single Chip Multiprocessor", Technical Report of IPSJ,ARC-130-5, Aug. 1998.
  127. D. Inaishi, K. Kimura, K. Fujimoto, W. Ogata, M. Okamoto, H. Kasahara, "A Cache Optimization with Earliest Executable Condition Analysis", Technical Report of IPSJ, ARC-130-6, Aug. 1998.
    128. 1997
  128. Yoshida, K. Koshizuka, M. Okamoto, H. Kasahara, "Data-Localization for Fortran Hierarchical Macro-Dataflow Processing", IPSJ SIG Notes,97-ARC-125-2, Aug. 1997.
  129. T. Tobita, H. Kasahara, "Evaluation of a Practical Parallel Optimization Algorithm for the Minimum Execution-Time Multiprocessor Scheduling Problem", Technical Report of IEICE, CPSY97-39, Aug. 1997.
  130. K. Kimura, S. Hashimoto, M. Kogou, W. Ogata, H. Kasahara, "A Macro Task Dynamic Scheduling Algorithm with Overlapping of Task Processing and Data Transfer", Technical Report of IEICE, CPSY97-40, Aug. 1997.
  131. K. Iwai, T. Fujiwara, T. Morimura, H. Amano, K. Kimura, W. Ogata, H. Kasahara, "Multi-processor system for Multi-grain Parallel Processing", Technical Report of IEICE, CPSY97-46, Aug. 1997.
  132. M. Obata, Y. Maekawa, S. Wakao, T. Onuki, H. Kasahara, "Parallel Processing of Hybrid Finite Element and Boundary Element Method for Electro-magnetic field analysis", IPSJ SIG Notes, 97-HPC-67-3, Aug. 1997.
  133. T. Tobita, H. Kasahara, "Performance Evaluation of a Practical Parallel Optimization Multiprocessor Scheduling Algorithm PDF/HIS", IPSJ SIG Notes, Vol. 97, No. 113, pp.13-18, Nov. 1997.
  134. W. Ogata, T. Yamamoto, M. Mizuno, K. Kimura, H. Kasahara, "Implementation of FPGA Based Architecture Test Bed For Multi Processor System", IPSJ SIG Notes, 98-ARC-128-14, Mar. 1998.
    135. 1996
  135. Yoshida, K. Koshizuka, W. Ogata, H. Kasahara, "A Near-Fine-Grain Task Scheduling Scheme for Multi-Grain Data-Localization", Technical Report of IEICE, CPSY96-66, Aug. 1996.
  136. K. Fujimoto, S. Hashimoto, H. Kasahara, "Parallelizing Compiler with Optimization of Overlapping of Data Transfer and Task Processing", Technical Report of IEE Japan, IP-96-24, Sep. 1996.
  137. W. Ogata, A. Yoshida, M. Okamoto, H. Kasahara, "Optimization of Data Transfer Order for Near Fine Grain Parallel Processing without Explicit Synchronization Code", Technical Report of IEE Japan, IP-96-29, Sep. 1996.
  138. Y. Maekawa, T. Sakamoto, M. Obata, S. Wakao, H. Kasahara, T. Onuki, "Parallel Processing Scheme of the Hybrid Finite Element and Boundary Element Method", Technical Report of IEE Japan, IP-96-27, Sep. 1996.
  139. M. Okamoto, K. Aida, A. Yoshida, H. Kasahara, S. Narita, "Development of a Practical Level Multi-Grain FORTRAN Compiler", SIG Notes of IPSJ, Oct. 1996.
  140. S. Wakao, M. Hori, Y. Maekawa, T. Sakamoto, H. Kasahara, T. Onuki, "The Application of Parallel Processing to The Hybrid FE-BE Analysis", Technical Report of IEE Japan, SA-96-10, RM-96-60, 1996
  141. S. Hashimoto, K. Fujimoto, M. Okamoto, H. Kasahara, "A Macro Task Scheduling Method of Overlapping of Data Transfer and Task Processing", Technical Report of IEICE, CPSY96-107, Jan. 1997.
  142. K. Aida, H. Kasahara, S. Narita, "Evaluation of a Scheduling Scheme of Parallel Jobs on a Multiprocessor System", IPSJ SIG Notes OS-73-13, Aug. 1996.
    143. 1995
  143. Y. Maekawa, M. Takai, T. Ito, K. Nishikawa, H. Kasahara, "A Hierarchical Parallel Processing Scheme of Circuit Simulation", SIG Notes of IEE, CPSY95-22, pp.87-94, 1995
    144. 1994
  144. A. Yoshida, S. Maeda, W. Ogata, H. Kasahara, "A Data-Localization Scheme among Doall/Sequential Loops for Macro-Dataflow Computation", Technical Report of IEE Japan, IP-94-40, Dec. 1994.
  145. W. Ogata, M. Oota, A. Yoshida, M. Okamoto, H. Kasahara, "Compilation Scheme for Near Fine Grain Parallel Processing without Synchronization on Multiprocessor System OSCAR", SIG Notes of IEE, IP-94-41, Dec. 1994.
  146. Y. Maekawa, M. Takai, T. Itoh, T. Nishikawa, H. Kasahara, "Parallel Processing Scheme of Electronic Circuit Simulation Using Circuit Tearing", SIG Notes of IEE, IP-94-44, Dec. 1994.
  147. K. Aida, M. Okamoto, H. Kasahara, S. Narita, "A Multi-job Execution Scheme for Macro-dataflow Computation", SIG Notes of IPSJ, OS-65-4, Jul. 1994.
  148. K. Nakano, H. Kasahara, "Parallel Search Scheme for Fast Vector Quantization with Sorted Codebook", Technical Report of IEICE, CPSY94-42, Jul. 1994.
  149. K. Aida, M. Okamoto, H. Kasahara, S. Narita, "Scheduling Scheme among Hierarchically Parallel Executed Jobs", SIG Notes of IPSJ, ARC-111-1, Mar. 1995.
    150. 1993
  150. A. Yoshida, S. Maeda, W. Ogata, M. Okamoto, H. Honda, H. Kasahara, "A Data-Localization Scheme for Macro-Dataflow Computation", Technical Report of IEICE, Vol. 93, No. 180 (CPSY93-23), pp.81-88, Aug. 1993.
  151. K. Nakano, H. Kasahara, "Parallel Processing of Non-linear Equations Solution on Multiprocessor Systems -Load Flow Calculation as an Example-", Technical Report of IEICE, Vol. 93, No. 302 (CPSY93-36), pp.9-15, Nov. 1993.
  152. K. AIDA, K. IWASAKI, K. MATSUMOTO, M. OKAMOTO, H. KASAHARA, S. NARITA, "Performance Evaluation of Macro-dataflow Computation on Shared Memory Multi-processor System", Technical Report of IPSJ, ARC-105-9, HPC-50-9, Mar. 1994.
    153. 1992
  153. M. Okamoto, K. Aida, W. Ogata, A. Yoshida, H. Honda, H. Kasahara, "A HIERARCHICAL MACRO-DATAFLOW COMPUTATION SCHEME OF FORTRAN PROGRAMS", SIG Notes of IPSJ, Vol. 92, No. 64 (ARC-95), pp.105-112, Aug. 1992.
  154. W. Ogata, M. Okamoto, H. Honda, H. Kasahara, S. Narita, "Near Fine Grain Parallel Processing on a Multiprocessor System Without Synchronization", Technical Report of IEICE, Vol. 92, pp.59-66, Oct. 1992.
  155. Yoshida, M. Okamoto, K. Aida, W. Ogata, H. Honda, H. Kasahara, "OSCAR Fortran Multi Grain Parallelizing Compiler", SIG Notes of IPSJ, Vol. 92, No. 85 (PRG-9), pp.71-78, Oct. 1992.
  156. K. Aida, K. Matsumoto, M. Okamoto, A. Yoshida, H. Honda, H. Kasahara, S. Narita, "Evaluation of Fortran Macro-dataflow Computation on a Multi-processor Supercomputer", Technical Report of IEICE, Vol. 92, No. 172 (CPSY92-13), pp.33-40, Aug. 1992.
    157. 1991
  157. K. Fujiwara, K. Shiratori, M. Suzuki, H. Kasahara, "Scheduling Algorithms Considering Data-preloading and Data-poststoring for Hierarchical Memory Multiprocessor Systems", Technical Report of IEICE, Vol. 91, No. 130 (CPSY91-14), pp.83-90, Jul. 1991.
  158. Y. Maekawa, M. Tamura, W. Premchaiswadi, H. Kasahara, S. Narita, "Parallel Processing of Direct Solution Method for Random Sparse Matrix", Technical Report of IEICE, Vol. 91, No. 130 (CPSY91-17), pp.107-114, Jul. 1991.
  159. K. Aida, M. Okamoto, A. Yoshida, H. Honda, H. Kasahara, "Schemes for decomposition and fusion of macrotasks in the macro-dataflow computation", Technical Report of IEICE, Vol. 91, No. 130 (CPSY91-30), pp.205-212, Jul. 1991.
  160. H. Honda, M. Okamoto, K. Aida, H. Kasahara, "Implementation of OSCAR/Fortran Compiler", SIG Notes of IPSJ, Vol. 91, No. 100 (ARC-91), pp.13-20, Nov. 1991.
  161. M. Okamoto, K. Aida, H. Honda, H. Kasahara, "A multi-grain parallel processing of Fortran programs", Technical Report of IEICE, Vol. 91, No. 365 (CPSY91-55), pp.23-30, Dec. 1991.
  162. A. Yoshida, K. Aida, M. Okamoto, H. Honda, H. Kasahara, "Fortran Macro-dataflow Computation on OSCAR", Technical Report of IEICE, Vol. 91, No. 463 (CPSY91-69), pp.55-62, Jan. 1992.
  163. H. Torii, M. Tamura, Y. Maekawa, Y. Yamamoto, H. Kasahara, S. Narita, "A PARALLEL PROCESSING SCHEME FOR REAL TIME SIMULATION OF CONTINUOUS-AND DISCRETE-TIME CONTROL SYSTEM", Technical Report of IEICE, Vol. 92, No. 28 (CPSY91-80), pp.67-74, Mar. 1992.
    164. 1990
  164. W. Premchaiswadi, H. Honda, H. Kasahara, S. Narita, "PARALLEL PROCESSING SCHEME OF THE SOLUTION OF STIFF NONLINEAR ORDINARY DIFFERENTIAL ALGEBRAIC EQUATIONS ON OSCAR", SIG Notes of IPSJ, Vol. 90, No. 60(ARC-83), pp.85-90, 1990
  165. H. Kasahara, H. Tanaka, K. Itoh, "Parallelized Optimizing Multiprocessor Scheduling Algorithm", SIG Notes of IPSJ, Vol. 90, No. 60 (ARC-83), pp.91-96, 1990
  166. H. Kasahara, H. Honda, W. PREMCHAISWADI, A. Ogura, A. Mogi, S. Narita, "PARALLEL PROCESSING OF NEAR FINE GRAIN TASKS ON OSCAR (Optimally Scheduled Advanced Multiprocessor)", SIG Notes of IPSJ, Vol. 90, No. 60(ARC-83), pp.97-102, 1990
    167. 1989
  167. H. Honda, M. Hirota, Y. Irie, M. Suzuki, H. Kasahara, S. Narita, "Implementation and Performance Evaluation of Fortran Parallel Processing System on Oscar", Technical Report of IEICE, Vol. 89, No. 168 (CPSY89 89-57), 1989
  168. M. Kai, T. Shimmei, K. Kobayashi, H. Kasahara, H. Iizuka, "Improvement in Hierarchical Pincers Attack Search for Or Parallel Processing of Prolog", Technical Report of IEICE, Vol. 89, No. 168 (CPSY89 45-58), 1989
    169. 1988
  169. H. Honda, S. Mizuno, M. Hirota, H. Kasahara, "A parallel processing scheme of Fortran programs on OSCAR's processor cluster", Technical Report of IEICE, Vol. 88, No. 155, Apr. 1988.
    170. 1987
  170. H. Kasahara, K. Nakano, H. Nakayama, E. Takane, S. Narita, "A Parallel Processing Scheme for the Calculation of Load Flow Using Scheduling Algorithms", Technical Report of IEE Japan, Vol. IP-87, No. 1-12, pp.111-120, Nov. 1987.
  171. H. Kasahara, H. Nakayama, E. Takane, S. Hashimoto, "Parallel Processing for The Solution of Sparse Linear Equations on OSCAR(Optimally SCheduled Advanced MultiprocessoR", SIG Notes of IPSJ, Vol. 88, No. 19(CA-70), 1988
  172. M. Kai, K. Kobayashi, H. Kasahara, "AN OR PARALLEL PROCESSING SCHEME OF PROLOG - HIERARCHICAL PINCERS ATTACK SEARCH -", SIG Notes of IPSJ, Vol. 88, No. 4(CA-69/MC-48), Jan. 1988.
  173. H. Kasahara, E. Takane, S. Narita, K. Tomizawa, N. Ohigashi, "PARALLEL PROCESSING OF THE SOLUTION OF ORDINARY DIFFERENTIAL EQUATIONS ON GENERAL PURPOSE MULTIPROCESSOR SYSTEM OSCAR", Technical Report of IEICE, Vol. 87, No. 349, Jan. 1988.
    174. 1986
  174. M. Kai, H. Kasahara, S. Narita, S. Honiden, N. Utihira, S. Tamura, "Parallel Processing of Prolog Based Concurrent Object Oriented Language Using Multiprocessor Scheduling Algorithms", Technical Report of IECE, Vol. 86, No. 10, Apr. 1986.
  175. H. Kasahara, T. Fujii, H. Honda, S. Narita, "Parallel Processing of Ordinary Differential Equations", SIG Notes of IPSJ, Jan. 1987.
  176. A. Ito, H. Kasahara, "Parallelized Optimal Multiprocessor Scheduling Algorithms", Technical Committee on Computation of IEICE, Mar. 1987.
    177. 1985
  177. H. Fujii, T. Yasui, K. Koumura, H. Kasahara, S. Narita, "Parallel Processing of Robot Dynamics Computation Using Multiprocessor Scheduling Algorithms", Technical Report of IECE, Vol. 85, No. 311, Mar. 1986.
  178. H. Wada, M. Kai, H. Kasahara, S. Narita, "An Application of DF/IHS to Minimizing Weighted Flow Time Multiprocessor Scheduling Problem", Technical Report of IECE, Vol. 85, No. 320, Mar. 1986.
    179. 1984
  179. H. Kasahara, M. Kai, T. Seki, H. Honda, S. Narita, "PARALLEL PROCESSING OF CONTINUOUS SYSTEMS SIMULATION USING MULTI-PROCESSOR SCHEDULING ALGORITHMS", Technical Report of IEICE, Vol. 84, No. 175, Oct. 1984.
  180. H. Kasahara, K. Koumura, T. Yasui, S. Narita, "PARALLEL PROCESSING OF ROBOT ARM CONTROL COMPUTATION USING MULTI-PROCESSOR SCHEDULING ALGORITHMS", Technical Report of IEICE, Vol. 84, No. 175, Oct. 1984.
  181. H. Kasahara, T. Yasui, K. Koumura, M. Kai, S. Narita, "Parallel Processing of Robot Control and Simulation using Multiprocessor Scheduling Algorithms", Technical Report of IEICE, Feb. 1985.
    182. 1983
  182. H. Kasahara and S. Narita, "A PRACTICAL OPTIMIZATION / APPROXIMATION ALGORITHM FOR MULTI-PROCESSOR SCHEDULING PROBLEM", Technical Report of IEICE, Vol. 83, No. 163, Oct. 1983.
    183. 1981
  183. H. Kasahara, N. Wakatsuki, S. Narita, "Parallel Processing Algorithm for Real Time Control and Simulation of Distributed Control System", Technical Report of IEE SIG on Information Processing, Feb. 1982.
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