2019

Papers

  1. Boma A. Adhi, Tomoya Kashimata, Ken Takahashi, Keiji Kimura, Hironori Kasahara, "Compiler Software Coherent Control for Embedded High Performance Multicore", IEICE Transaction on Electronics Special Section on “Low-Power and High-Speed Chips”, Vol. E103-C, No. 3, pp.85-97, Mar. 2020.
  2. Yoshitake Oki, Yuto Abe, Kazuki Yamamoto, Kohei Yamamoto, Tomoya Shirakawa, Akimasa Yoshida, Keiji Kimura, Hironori Kasahara, "Local Memory Mapping of Multicore Processors on an Automatic Parallelizing Compiler", IEICE Transaction on Electronics　Special Section on “Low-Power and High-Speed Chips”, Vol. E103-C, No. 3, pp.98-109, Mar. 2020.
  3. Reem Elkhouly, Mohammad Alshboul, Akihiro Hayashi, Yan Solihin, Keiji Kimura, "Compiler-support for Critical Data Persistence in NVM", ACM Transactions on Architecture and Code Optimization (TACO), Vol. 16, No. 4-54, Dec. 2019.
  4. Tomoya Kashimata, Toshiaki Kitamura, Keiji Kimura, Hironori Kasahara, "Cascaded DMA Controller for Speedup of Indirect Memory Access in Irregular Applications", IA^3 2019: 9th Workshop on Irregular Applications: Architectures and Algorithms, Nov. 2019.
  5. Yu Omori, Keiji Kimura, "Performance Evaluation on NVMM Emulator Employing Fine-Grain Delay Injection", The 8th IEEE Non-Volatile Memory Systems and Applications Symposium (IEEE NVMSA 2019), Aug. 2019.
  6. Tohma Kawasumi, Ryota Tamura, Yuya Asada, Jixin Han, Hiroki Mikami, Keiji Kimura, Hironori Kasahara, "Fast and Highly Optimizing Separate Compilation for Automatic Parallelization", The 2019 International Conference on High Performance Computing & Simulation (HPCS 2019), Jul. 2019.
  7. Mohammad Alshboul, Hussein Elnawawy, Reem Elkhouly, Keiji Kimura, James Tuck, Yan Solihin, "Efficient Checkpointing with Recompute Scheme for Non-volatile Main Memory", ACM Transactions on Architecture and Code Optimization (TACO), Vol. 16, No. 18, May. 2019.
  8. Boma A. Adhi, Masayoshi Mase, Yuhei Hosokawa, Yohei Kishimoto, Taisuke Onishi, Hiroki Mikami, Keiji Kimura, Hironori Kasahara, "Software Cache Coherent Control by Parallelizing Compiler", Lecture Notes in Computer Science, Vol. LNCS 11403. Springer, 2019, pp.17-25, 2019.

Articles

  1. Hironori Kasahara, ”Aiming for World Level Research Promotion Considering Safety and Environment″,Waseda Univ. Environmental Safety Center "Environment 40th anniversary edition ", pp.3, Nov.25,2019

Invited Talks

  1. Hironori Kasahara, "Green Multicore Computing", Hosted by Prof. Jean-Luc Gaudiot, Distinguished Professor, University of California, Irvine, California, USA, Feb. 21, 2020.
  2. Hironori Kasahara, Strengthening Research at Waseda University" , Ministry of Education, Culture, Sports, Science and Technology　Research Funds Committee, Tokyo,Japan, Jan. 29, 2020.
  3. Hironori Kasahara, "Activities as IEEE Computer Society President 2018 and Waseda Open Innovation Valley Project" , Seminar in Toshiba Corporate Research & Development Center, Kawasaki, Japan, Jan. 23, 2020.
  4. Hironori Kasahara, "An Approach to Research Enhancement in Waseda University -- Waseda Open Innovation Valley Project --", Waseda University Trustee Forum, Tokyo,Japan, Dec. 07, 2019.
  5. Hironori Kasahara, "About Activities of IEEE Computer Society 2018 as President and the Concept of Waseda Open Innovation Valley", 20th Anniversary Waseda Univ. DCC(Digital Campus Consortium) Invited talk, Tokyo,Japan, Nov. 27. 2019.
  6. Hironori Kasahara, "Automatic Parallelization by OSCAR　Compiler for NEC SX-Aurora TSUBASA", NEC Aurora Community Meeting at SC19( IEEE ACM Super Computing2019), Denver, USA, Nov. 18, 2019.
  7. Hironori Kasahara, "Parallelising Compiler for Green Multicore Computing", Hosted by Prof. Jeremy Gibbons, Department of Computer Science, Oxford University , Oxford,UK, Nov. 13, 2019.
  8. Hironori Kasahara, "Future of Green Multicore Computing", Hitachi Academic System Study Group, Tokyo, Japan, Sep. 26, 2019.
  9. Hironori Kasahara, "Plenary Panel: Meeting of the Alliances", The(Times Higher Education)World Academic Summit 2019 in Zurich, Zurich, Switzerland, Sep. 10, 2019.
  10. Hironori Kasahara, "Parallel Processing of MATLAB and Simulink Simulation and Control on Multicore Processors", MathWorks Asia Research Summit, Tokyo, Japan, Sep. 06, 2019.
  11. Hironori Kasahara, "High Performance Computing and Medical Treatment", Japan Medical Association, Tokyo, Jul. 11, 2019.
  12. Hironori Kasahara, "Green Multicore Compiler", MPSoC Forum 2019, Tokyo, Jul. 08, 2019.
  13. Hironori Kasahara, "Opening Remarks --Simon WRIGHT, Director - Programming, Japan House London --", SYMPOSIUM:Classical Arts x Digital Technologies, London, UK, Jun. 29, 2019.

Technical Reports

  1. Toma Kawasumi, Tilman Priesner, Masato Noguchi, Jixin Han, Hiroki Mikami, Takahiro Miyajima, Keishiro Tanaka, Keiji Kimura, Hironori Kasahara, "Extensions of OSCAR Compiler for Parallelizing C++ Programs", Information Processing Society of Japan, Special Interest Group on System Architecture (ARC232@ETNET2020), Feb. 2020.
  2. Yuta Tadokoro, Hiroki Mikami, Takeo Hosomi, Keiji Kimura, Hironori Kasahara, "Automatic Vector-Parallelization by Collaboration of Oscar Automatic Parallelizing Compiler and NEC Vectorizing Compiler", Information Processing Society of Japan, Special Interest Group on System Architecture (ARC232@ETNET2020), Feb. 2020.
  3. Kazuki Yamamoto, Kazuki Fujita, Tomoya Kashimata, Ken Takahashi, Boma A. Adhi, Toshiaki Kitamura, Akihiro Kawashima, Akira Nodomi, Yuji Mori, Keiji Kimura, Hironori Kasahara, "Consideration of Accelerator Cost Estimation Method in Multi-Target Automatic Parallelizing Compiler", Information Processing Society of Japan, Special Interest Group on System Architecture (ARC232@ETNET2020), Feb. 2020.
  4. Hikaru Nishida, Keiji Kimura, "NDCKPT: Transparent Check Pointing Mechanism on Non Volatile Memory by OS", Information Processing Society of Japan, Special Interest Group on System Architecture (ARC232@ETNET2020), Feb. 2020.
  5. Tetsuya Makita, Teppei Shishido, Yasutaka Wada, Keiji Kimura, "Investigation into Acceleration of Matrix-multiply in Homomorphic Encryption", Information Processing Society of Japan, Special Interest Group on System Architecture (ARC232@ETNET2020), Feb. 2020.
  6. Keiji Kimura, Kazuki Fujita, Kazuki Yamamoto, Tomoya Kashimata,Toshiaki Kitamura, Hironori Kasahara, "Automatically Parallelizing Compiler Cooperative OSCAR Vector Multicore", International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, Feb. 2020.

Poster Session / Academic Exhibition

  1. Kazuki Yamamoto, Kazuki Fujita, Yuta Tadokoro, Tomoya Kashimata, Hiroki Mikami, Boma A. Adhi, Yoshitake Ooki, Toshiaki Kitamura, Keiji Kimura, Hironori Kasahara, "OSCAR Automatic Parallelizing Compiler - Automatic Speedup and Power Reduction -", in ITBL Booth, IEEE ACM SC (Super Computing) 2019 Exhibition, Denver, Nov.18-21,2019
  2. Kazuki Yamamoto, Kazuki Fujita, Yuta Tadokoro, Tomoya Kashimata, Hiroki Mikami, Boma A. Adhi, Yoshitake Ooki, Toshiaki Kitamura, Keiji Kimura, Hironori Kasahara, "OSCAR Parallelizing & Power Reducing Compiler - Power is Reduced to 1/7 on ARM -", in ITBL Booth, IEEE ACM SC (Super Computing) 2019 Exhibition, Denver, Nov.18-21,2019
  3. Kazuki Yamamoto, Kazuki Fujita, Yuta Tadokoro, Tomoya Kashimata, Hiroki Mikami, Boma A. Adhi, Yoshitake Ooki, Toshiaki Kitamura, Keiji Kimura, Hironori Kasahara, "OSCAR Vector Multicore System - Platinum Vector Accelerator on FPGA -", in ITBL Booth, IEEE ACM SC (Super Computing) 2019 Exhibition, Denver, Nov.18-21,2019

Patents

　 Registration of patent

  1. "PARALLELIZING COMPILER PARALLELIZING COMPILATION APPARATUS, AND METHOD OF CREATING A PARALLEL PROGRAM", 6600888(JP Patent), Oct.18,2019.
  2. "METHOD OF GENERATING CODE EXECUTABLE BY PROCESSOR", 2508992(EP Patent), Jun.26,2019.
  3. "METHOD OF GENERATING CODE EXECUTABLE BY PROCESSOR", 602010059750.4(DE Patent), Jun.26,2019.
  4. "METHOD OF GENERATING CODE EXECUTABLE BY PROCESSOR", 2508992(GB Patent), Jun.26,2019.
  5. "PROCESSOR CORES AND PROCESSOR SYSTEM", 6525286(JP Patent), May.17,2019.

　 Published applications for patent

  1. "METHOD OF MANAGING A STORAGE AREA OF A MEMORY IN A MULTIPROCESSOR SYSTEM", 3486767(EP Publication), May.22,2019. [Registration of patent:3486767(EP Patent), Jul.22,2020.]
  2. "METHOD OF MANAGING A STORAGE AREA OF A MEMORY IN A MULTIPROCESSOR SYSTEM", 3486767(DE Publication), May.22,2019. [Registration of patent:602010065015.4(DE Patent), Jul.22,2020.]
  3. "METHOD OF MANAGING A STORAGE AREA OF A MEMORY IN A MULTIPROCESSOR SYSTEM", 3486767(GB Publication), May.22,2019. [Registration of patent:3486767(GB Patent), Jul.22,2020.]

Award

  1. Yu Omori, "Waseda Univ. Department of Communications and Computer Engineering/ Department of Computer Science and Communications Engineering Award", Mar. 2020.
  2. Hikaru Nishida, "Information Processing Society of Japan, SIGARC （Special Interest Group on System Architecture), Young Researcher Award", Mar. 2020.
  3. Hironori Kasahara, "IEEE Computer Society Spirit of the Computer Society Award", Oct. 2019.
  4. Toma Kawasumi, "Waseda Univ. Department of Communications and Computer Engineering/ Department of Computer Science and Communications Engineering Award", Sep. 2019.

Media

　Articles in Newspapers

  1. Nikkan Kogyo Shimbun, "Laser Kasahara-san --Innovation Day--“, Oct.09,2019.
  2. Nikkan Kogyo Shimbun, "Joining Forces for New Industry Creation --Waseda Open Innovation Valley Connecting Research Facility--", Sep.19,2019.

　Articles

  1. Waseda Univ. HP, "Waseda signs agreement with University of Tokyo to fast track social change" , Mar.30.2020.
  2. Science Magazine, Vol. 367, Issue.6479, "How Waseda University is Helping Japan Stay Competitive" , Feb.14.2020.
  3. Science Magazine, Vol.367, Issue.6478, "Robots, Baseball, and Bilingualism Embody Waseda University' s Culture of Scholarship" , Feb.07.2020.
  4. Science Magazine, Vol.367, Issue.6476, "Theoretical and Applied Research Help Cut Pollution" , Jan.24.2020.
  5. University of Oxford HP, "--Parallelising Compiler for Green Multicore Computing-- Professor Hironori Kasahara (Waseda University)" , Dec.17,2019.
  6. Between , ‘E. Tsutsui, “World Academic Summit Participation Report" 'pp.8-9 , Nov.12,2019.
  7. 騰訊高校合作, 「犀牛鳥学聞 | 早稲田大学笠原副校長一行訪問騰訊」 , Nov.05,2019.
  8. LINK-J Interview Column, The Only Way to Reflourish an Industrial Nation Japan is Industry-Academia Collaboration , Oct.17,2019.
  9. Computer, IEEE CS, "Gallery of 2019 Winners: IEEE Computer Society's Board of Governors Honors Newest Award Recipients" , Jun.10,2019.
  10. Computer, IEEE CS, "IEEE Computer Society Awards Presentations" , Jun.05,2019.
  11. Waseda Univ. HP, "Research Visit to Maeda Corporation ICI Integrated Research Center on May 7, 2019 " , May.19,2019.
  12. Springer Nature Switzerland AG 2019, LNCS (Lecture Notes in Computer Science) 11403, Languages and Compilers for Parallel Computing, -- 30th International Workshop, LCPC 2017, College Station, TX, USA, October 11?13, 2017, Revised Selected Papers, "Multigrain Parallelization and Compiler/Architecture Co-design for 30 Years, Hironori Kasahara", pp.22 , Apr.2019.

　Web News

  1. Samueli School of Engineering University of California, Irvine, "EECS Seminar: Green Multicore Computing" , Feb.21.2020.
  2. American Association for the Advancement of Science, "Waseda University: Driving positive change in science and society" , Jan.24.2020.
  3. Waseda Alumni Nishitokyo-tomonkai Home Page, "Waseda University SEVP Hironori Kasahara, actively working in the World, talked about Waseda Open Innovation Valley Project: For strengthening Research in Waseda University in the Waseda Counsellor Forum on Dec. 7, 2019", Dec.07,2019.
  4. Twitter, Waseda Univ., "Thank you Prof. Vivek Sarkar @GerogiaTech GT Computing for visiting @Waseda_Univ and giving a talk" , Mar.26,2019.