2017

Books

  1. Cristina Seceleanu, Hironori Kasahara, Tiberiu Seceleanu, "Message from the CAP 2017 Organizing Committee", IEEE COMPSAC 2017 (The 41th IEEE Computer Society International Conference on Computers, Software & Applications), Jul. 2017.

Papers

  1. Boma A. Adhi, Masayoshi Mase, Yuhei Hosokawa, Yohei Kishimoto, Taisuke Onishi, Hiroki Mikami, Keiji Kimura, Hironori Kasahara, "Software Cache Coherent Control by Parallelizing Compiler", 30th International Workshop on Languages and Compilers for Parallel Computing(LCPC), Oct. 2017.
  2. Hironori Kasahara, Keiji Kimura, Boma A. Adhi, Yuhei Hosokawa，Yohei Kishimoto,　Masayoshi Mase, "Multicore Cache Coherence Control by a Parallelizing Compiler", IEEE COMPSAC 2017 (The 41th IEEE Computer Society International Conference on Computers, Software & Applications), Jul. 2017.

Articles

  1. Hironori Kasahara, "Satisfaction and Sustainability", Computer IEEE Computer Society , pp4-6, Jan. 2018
  2. Hironori Kasahara, "IEEE Division VIII Delegate/Director Candidates", Computer, IEEE Computer Society, Vol.50, Issue 8, pp.94-95, Aug. 2017
  3. Hironori Kasahara, "IEEE President-Elect Candidates Address Computer Society Concerns", Computer, IEEE Computer Society, Vol.50, Issue 8, pp.96-100, Aug. 2017
  4. Cristina Seceleanu, Hironori Kasahara, Tiberiu Seceleanu, "Message from the CAP 2017 Organizing Committee", IEEE COMPSAC 2017 (The 41th IEEE Computer Society International Conference on Computers, Software & Applications), Jul. 2017

Invited Talks

  1. Hironori Kasahara, "OSCAR Automatic Parallelizing and Power Reducing Multicore Compiler for Realtime Embedded to High Performance Computing", Mitsubishi Electric Information Technology Research Institute, Ofuna, Japan, Mar. 14. 2018.
  2. Hironori Kasahara, "Future of High Performance Low Power Multicore Computing", The 80th National Convention of IPSJ , 東京, Mar. 14. 2018.
  3. Hironori Kasahara, "HPGC Round table", International Symposium on Future of High Performance Green Computing 2018 (HPGC2018) , Tokyo, Japan, Mar. 08. 2018.
  4. Hironori Kasahara, "Future of High Performance Green OSCAR Multicore Computing", International Symposium on Future of High Performance Green Computing 2018 (HPGC2018) , Tokyo, Japan, Mar. 08. 2018.
  5. Hironori Kasahara, "High Performance Green Multicore Computing", hosted by Prof. Kastury, University of South Florida, Tampa, USA, Feb. 12. 2018.
  6. Hironori Kasahara, "High Performance Low Power OSCAR Multicore and Compiler", hosted by Prof. David Kuck, University of Texas, Austin, USA, Feb. 09. 2018.
  7. Hironori Kasahara, "Green Multicore Computing: Co-design of Software and Architecture", Korea Software Congress 2017, Korea, Dec. 21. 2017.
  8. Hironori Kasahara, "Future of High Performance & Low Power Multicore Technology", SEMICON Japan, Tokyo, Japan, Dec. 17. 2017.
  9. Hironori Kasahara, "Green Multicore Computing and Industry Collaboration", Ministry of foreign Affairs of Japan Russian IT Industry Japan Visiting Program, Tokyo, Japan, Nov. 30. 2017.
  10. Hironori Kasahara, "IEEE CS President Elect 2017, President 2018 Address", IEEE International Conference on Network and Service Management, Tokyo, Japan, Nov. 29. 2017.
  11. Hironori Kasahara, "World Tidal Current Zed by Computer Science", Waseda University "Advanced Data Related Human Resource Development Program" Symposium Kick off, Tokyo, Japan, Nov. 27. 2017.
  12. Hironori Kasahara, "Performance and Low Power for Multicores", University of Cambridge Astrophysics Group SKA(Square Kilometre Array telescope project), Cambridge, UK, Oct. 26. 2017.
  13. Hironori Kasahara, "Multigrain Parallelization and Compiler/Architecture Co-design for 30 Years with LCPC", 30th International Workshop on Languages and Compilers for Parallel Computing(LCPC), College Station, Texas, U.S.A., Oct. 12. 2017.
  14. Hironori Kasahara, "Software and Hardware for High Performance and Low Power Homogeneous and Heterogeneous\ Multicore Systems", CPS Summer School 2017, Sardinia, Italy, Sep. 28. 2017.
  15. Hironori Kasahara, "Inauguration of IEEE Computer Society President 2018 and Industry and Academia Research and Development Collaboration on Green Multicores", Council of Departments of Computer Science & Engineering in Japanese Universities, Tokyo, Japan, Jul. 21. 2017.
  16. Hironori Kasahara, "Latest Trends in Automatic Parallelization and Power Reduction Compiler", Symposium on Embedded Multicores and Automatic Parallelizing and Power Consumption Reducing Compiler in Post-Moore Generation, Tokyo, Japan, Jul. 19. 2017.
  17. Hironori Kasahara, "Future of Green Multicore Computing", hosted by Prof. Stefano Zanero, Politecnico di Milano, Milano, Italy, Jul. 10. 2017.
  18. Hironori Kasahara, "COMPSAC 2017 Plenary Panel Future of Computing: Exciting Research in Computers, Software and Applications Green Multicore Computing", IEEE COMPSAC 2017 (The 41th IEEE Computer Society International Conference on Computers, Software & Applications), Torino, Italy, Jul. 07. 2017.
  19. Hironori Kasahara, "Automatic Cache and Local Memory Optimization for Multicores", 17th INTERNATIONAL FORUM ON MPSoC for software-defined hardware, Annecy, France, Jul. 04. 2017.
  20. Hironori Kasahara, "Cool Chips, Low Power Multicores, Open the Way to the Future", IEEE Symposium on Low-Power and High-Speed Chips(COOL CHIPS 20),20th Anniversary Panel, Yokohama, Japan, Apr. 20. 2017.
  21. Hironori Kasahara, "2017 COOL Chips 20 Cerebration for the 20th Anniversary of IEEE Symposium on Low-Power and High-Speed Chips", IEEE Symposium on Low-Power and High-Speed Chips (COOL CHIPS 20), Opening Address, Yokohama, Japan, Apr. 20. 2017.
  22. Hironori Kasahara, "The Low Power Multicore and Its Software for Embedded to High Performance Computing", 3rd IEEE PCSC '17 (IEEE Pakistan Computer Society Congress), Key Note Speech, IEEE Computer Society Karachi Section, Arts Auditorium University of Karachi (UOK), Karachi, Pakistan, Apr. 08. 2017.

Technical Reports

  1. Ken Takahashi, Satoshi Karino,Kazuki Miyamoto, Takumi Kawata, Tomoya Kashimata,Tetsuya Makita, Toshiaki Kitamura, Keiji Kimura, Hironori Kasahara, "Development of Compilation Flow and Evaluation of OSCAR Vector Multicore Architecture", The 80th National Conversion of Information Processing Society of Japan, Mar. 2018.
  2. Tomoya Kashimata, Satoshi Karino, Kazuki Miyamoto, Takumi Kawata, Ken Takahashi, Tetsuya Makita, Toshiaki Kitamura, Keiji Kimura, Hironori Kasahara, "FPGA implementation of OSCAR Vector Accelerator", The 80th National Conversion of Information Processing Society of Japan, Mar. 2018.
  3. Kazuki Miyamoto, Tetsuya Makita, Ken Takahashi, Tomoya Kashimata, Takumi Kawada, Satoshi Karino, Toshiaki Kitamura, Keiji Kimura, Hironori kasahara, "Automatic parallelizing and vectorizing compiler framework for OSCAR vector multicore processor", Information Processing Society of Japan, Special Interest Group on System Architecture (ARC222@ETNET2018), Mar. 2018.
  4. Tomoya Shirakawa, Yuto abe, Yoshitake Ooki, Akimasa Yoshida, Keiji Kimura, Hironori Kasahara, "Automatic Local Memory Management Using Hierarchical Adjustable Block for Multicores and Its Performance Evaluation", Technical Report of IPSJ, 2017-ARC-220 (DesignGaia2017), Nov. 2017.
  5. Tomoya Shirakawa, Yuto abe, Yoshitake Ooki, Akimasa Yoshida, Keiji Kimura, Hironori Kasahara, "Automatic Local Memory Management Using Hierarchical Adjustable Block for Multicores and Its Performance Evaluation", Technical Report of IPSJ, 2017-ARC-220 (DesignGaia2017), Nov. 2017.

Poster Session / Academic Exhibition

  1. Ando Kazumasa, Tomoya Shirakawa, Yuya Nakada, Yuki Shimizu, Hiroki Shimizu, Yuto Abe, Hideo Yamamoto, Mamoru Shimaoka, Hiroki Mikami, Keiji Kimura, Hironori Kasahara, "OSCAR Automatic Parallelizing Compiler-[Automatic Power Reduction of OpenCV Face Detection by OSCAR Compiler, Automatic parallelization of applications generated from MATLAB / Simulink(on Intel, arm, Renesas Chips)by OSCAR compiler]", Embedded Technology 2017, Pacifico Yokohama, Nov. 15. 2017.
  2. Hiroki Mikami, Boma Anantasatya Adhi, Tomoya Kashimata, Satoshi Karino, Kazuki Miyamoto, Takumi Kawata, Ken Takahashi, Tetsuya Makita, Tomoya Shirakawa, Yoshitake Oki, Toshiaki Kitamura, Keiji Kimura, Hironori Kasahara, "OSCAR Automatic Parallelizing Compiler -Automatic Speedup and Power Reduction-[Parallel Processing of MATLAB/Simulink by OSCAR Compiler on Intel, ARM & Renesas multi cores, OSCAR Parallelizing & Power Reducing Compiler-Power is Reduced to 1/7 on ARM-,OSCAR Vector Multicore System -Platinum Vector Accelerator on FPGA-]", in ITBL Booth, IEEE ACM SC (Super Computing) 2017 Exhibition, Denver, Nov. 2017

Patents

　Registration of patent

  1. "METHOD OF PROVIDING A NON-CACHEABLE AREA IN MEMORY", 9928057(US Patent), Mar.27.2018.
  2. "PROCESSOR, ACCELERATOR, AND DIRECT MEMORY ACCESS CONTROLLER WITHIN A PROCESSOR CORE THAT EACH READS/WRITES A LOCAL SYNCHRONIZATION FLAG AREA FOR PARALLEL EXECUTION", 9846673(US Patent), Dec.19.2017.
  3. "PARALLELIZATION COMPILING METHOD, PARALLELIZATION COMPILER, PARALLELIZING COMPILE APPARATUS, AND ONBOARD APPARATUS", 9760355(US Patent), Sep.12.2017.
  4. "ACCELERATOR AND PROCESSOR SYSTEM", I597661(TW Patent), Sep.01.2017.
  5. "PROCESSOR SYSTEM AND ACCELERATOR", ZL201280065692.7(CN Patent), Jul.04.2017.

　Published applications for patent

  1. "PROCESSOR, ACCELERATOR, AND DIRECT MEMORY ACCESS CONTROLLER WITHIN A CORE READING/WRITING LOCAL SYNCHRONIZATION FLAG AREA FOR PARALLEL EXECUTION", 2018/0060275(US Publication), Mar.01.2018. [Registration of patent:10095657(US Patent), Oct.09.2018.]
  2. "PROCESSOR CORES AND PROCESSOR SYSTEM", 2017-091589(JP Publication), May.25.2017. [Registration of patent:6525286(JP Patent), May.17.2019.]

Award

  1. Yuki Shimizu, "DICOMO Young Researcher Award", Jul. 2017.
  2. Yuki Shimizu, "DICOMO Excellent Paper Award", Jul. 2017.

Media

　Articles

  1. IEEE計算机協会, "会見IEEE計算机協会2018年主席笠原博德。他的計劃是什麼?", Mar.09.2018.
  2. KSLA NEWS12, "Computer and IEEE Micro Magazines Highlight Intel's Loihi, a Revolutionary Neuromorphic 'Self-Learning' Chip" , Mar.08.2018.
  3. Computer, IEEE CS, "Meet Hironori Kasahara, The 2018 President Of The IEEE Computer Society. What Are His Plans?", Mar.07.2018.
  4. Interface, IEEE CS, "Now Accepting Nominations for Computer Society Officer Positions" , Mar.01.2018.
  5. EAJ News, "A new member of the Engineering Academy of Japan", Dec.01.2017.
  6. IEEE TOKYO , "New Fellow Awards ceremony and social gathering in 2017" , May.12.2017.

　Articles in Web

  1. Prabook, "Hironori Kasahara Edit Profile computer science educator" , Jan.01.2018.
  2. Dipartimento di Elettoronica, "Future of Green Multicore Computing" , Jul.10.2017.
  3. COMPSAC 2017, "Message from the CAP 2017 Organizing Committee" , Jul.07.2017.
  4. 17th INTERNATIONAL FORUM ON MPSoC, "Automatic Cache and Local Memory Optimization for Multicores" , Jul.03.2017.
  5. Waseda Univ. HP, "Second half of 2016 Access Ranking for Research Related Articles Waseda's Research Power has been Highly Evaluated by the World" , Apr.26.2017.
  6. COOL CHIPS2017, "Cool Chips, Low Power Multicores, Open the Way to the Future" , Apr.19.2017.
  7. NIKKEI Technology Online, "Parallel software technology going ahead 5 years, the huge market beyond Death Valley" , Apr.19.2017.
  8. Waseda Univ. HP, "Beyond the future created by computers -- International SISA Workshop 'Extreme-Scale HPC and Big Data Systems: A Pathway to Their Convergence and Beyond' --" , Apr.01.2017.
  9. Waseda Univ. HP, "International Workshop on 'Strategic Computing Initiative' SISA 2017 was held in Waseda Univ., Green Computing Center" , Apr.01.2017.