2007

Papers

  1. Hironori Kasahara, "Multicore Processors for Consumer Electronics", The Journal of IEE of Japan, Vol. 128, No. 3, pp.172-175, Mar. 2008.
  2. Masayuki Ito, Toshihiro Hattori, Yutaka Yoshida, Kiyoshi Hayase, Tomoichi Hayashi, Osamu Nishii, Yoshihiko Yasu, Atsushi Hasegawa, Masashi Takada, Masaki Ito, Hiroyuki Mizuno, Kunio Uchiyama, Toshihiko Odaka, Jun Shirako, Masayoshi Mase, Keiji Kimura, Hironori Kasahara, "An 8640 MIPS SoC with Independent Power-off Control of 8 CPU and 8 RAMS by an Automatic Parallelizing Compiler", Proc. of IEEE International Solid State Circuits Conference (ISSCC2008), Feb. 2008.
  3. Hiroaki Shikano, Masaki Ito, Kunio Uchiyama, Toshihiko Odaka, Akihiro Hayashi, Takeshi Masuura, Masayoshi Mase, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, "Software-Cooperative Power-Efficient Heterogeneous Multi-Core for Media Processing", Proc. of 13th Asia and South Pacific Design Automation Conference (ASP-DAC 2008), Jan. 2008.
  4. Jun Shirako, Munehiro Yoshida, Naoto Oshiyama, Yasutaka Wada, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara, "Performance Evaluation of Compiler Controlled Power Saving Scheme", Lecture Notes in Computer Science, Springer, Vol. 4759, pp.480-493, Jan. 2008.
  5. Jun Shirako, Hironori Kasahara, Vivek Sarkar, "Language Extensions in Support of Compiler Parallelization", Proc. of The 20th International Workshop on Languages and Compilers for Parallel Computing (LCPC2007), University of Illinois at Urbana-Champaign, Siebel Center for Computer Science, Urbana, Illinois, Oct. 2007.(pdf)
  6. M. Mase, D. Baba, H. Nagayama, H. Tano, T. Masuura, T. Miyamoto, J. Shirako, H. Nakano, K. Kimura, H. Kasahara, "Multigrain Parallelization of Restricted C Programs on SMP Servers and Low Power Multicores", The 20th International Workshop on Languages and Compilers for Parallel Computing (LCPC2007), Oct. 2007.
  7. Masaki Ito, Takashi Todaka, Takanobu Tsunoda, Hiroshi Tanaka, Tomoyuki Kodama, Hiroaki Shikano, Masafumi Onouchi, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, "Heterogeneous Multiprocessor on a Chip Which Enables 54x AAC-LC Stereo Encoding", Proc. of 2007 Symposia on VLSI TEchnology and Circuits, Jun. 2007.
  8. Hiroaki Shikano, Yuki Suzuki, Yasutaka Wada, Jun Shirako, Keiji Kimura and Hioronori Kasahara, "Performance Evaluation of MP3 Audio Encoder on OSCAR Heterogeneous Chip Multicore Processor", Trans. of IPSJ on Computing Systems, Vol. 48, No. SIG8（ACS18), pp.141-152, May. 2007.
  9. Jun Shirako, Nato Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara, "Compiler Control Power Saving Scheme for Multi Core Processors", Lecture Notes in Computer Science, Springer, Vol. 4339, pp.362-376, May. 2007.

    　

Invited Talks

  1. Hironori Kasahara, "A Multigrain Parallelizing Compiler with Power Control for Multicore Processors", Google Headquarter, Hosted by Dr. Shih-wei Liao, 2008.2.5,10:00-11:00 (pdf)
  2. Hironori Kasahara, "A Multigrain Parallelizing Compiler with Power Control for Multicore Processors", Intel Headquarter, Hosted by Dr. Peng Tu, 2008.2.5,1:30-3:00 (pdf)
  3. Hironori Kasahara, "Advanced Parallelizing Compiler Technology for High Performance Low Power Multicores", VDEC Refresh Seminar, Tokyo Univ., Jan. 2008.
  4. Hironori Kasahara, "Low Power High Performance Multicores and Compiler Technology", The 5th Technology Link in W.T.L.O - For International Research Center in Collaboration of Industry and Academia, Waseda Univ., Oct. 2007.
  5. Hironori Kasahara, "How is specifically multicore programming different from traditional parallel computing? (Panel Discussion)", The 20th International Workshop on Languages and Compilers for Parallel Computing (LCPC2007), Univ. Illinois at Urbana-Champaign, Oct 11. 2007. (pdf)
  6. Hironori Kasahara, " A Multi-core Parallelizing Compiler for Low-Power High-Performance Computing ", Colloquium Electrical and Computer Engineering, Computer and Information Technology Institute, Computer Science, and Dean of Engineering, Duncan Hall, Rice University, Hosted by Prof. Vivek Sarkar, Monday, Oct 8, 2007
  7. Hironori Kasahara, "Multicore Innovation", Waseda Univ. 125 th & Faculty of Science and Engineering 100th Anniversary Symposium "Innovative Information, Electronics, and Optical technology", Sep. 2007. ,
  8. Hironori Kasahara, "Advanced Parallelizing Compiler Technologies for Embedded Multi-cores", DA Symposium 2007, Hamamatsu, Aug. 2007.

　

Technical Reports

  1. Takamichi Miyamoto, Kei Tamura, Hiroaki Tano, Hiroki Mikami, Saori Asaka, Masayoshi Mase, Keiji Kimura, Hironori Kasahara, "Parallelization for Multimedia Processing on Multicore Processors", Technical Report of IPSJ, 2007-ARC-175-05 (DesignGaia2007), Nov. 2007.   (pdf)
  2. Hiroaki Shikano, Masaki Ito, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Masafumi Onouchi, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, "Evaluation of Heterogeneous Multicore Architecture with AAC-LC Stereo Encoding", THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS, TECHNICAL REPORT OF IEICE. (ICD2007-71), Vol. 107, No. 195, pp.11-16, Aug. 2007.  (pdf)
  3. Yasutaka Wada, Akihiro Hayashi, Taketo Iyoku, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara, "A Hierarchical Coarse Grain Task Static Scheduling Scheme on a Heterogeneous Multicore", Technical Report of IPSJ, 2007-ARC-174-17(SWoPP2007), Aug. 2007. (pdf)
  4. Akihiro Hayashi, Taketo Iyoku, Ryo Nakagawa, Shigeru Matsumoto, Kaito Yamada, Naoto Oshiyama, Jun Shirako, Yasutaka Wada, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara, "Compiler Control Power Saving for Heterogeneous Multicore Processor", Technical Report of IPSJ, 2007-ARC-174-18(SWoPP2007), Aug. 2007. (pdf)
  5. Masayoshi Mase, Daisuke Baba, Harumi Nagayama, Hiroaki Tano, Takeshi Masuura, Takamichi Miyamoto, Jun Shirako, Hirofumi Nakano, Keiji Kimura, Tatsuya Kamei, Toshihiro Hattori, Atsushi Hasegawa, Makoto Sato, Masaki Ito, Toshihiko Odaka, Hironori Kasahara, "Mutligrain Parallel Processing in SMP Execution Mode on a Multicore for Consumer Electronics", Technical Report of IPSJ, 2007-ARC-173-05, May. 2007. (pdf)
  6. Kiyoshi hayase, Yutaka Yoshida, Tatsuya Kamei, Shinichi Shibahara, Osamu Nishii, Toshihiro Hattori, Atsushi Hasegawa, Masashi Takada, Naohiko Irie, Kunio Uchiyama, Toshihiko Odaka, Kiwamu Takada, Keiji Kimura, Hironori Kasahara, "A 4320MIPS four Processor-core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption", Technical Report of IPSJ, 2007-ARC-173-06, May. 2007.

　

Symposium

  1. Masayoshi Mase, Daisuke Baba, Harumi Nagayama, Hiroaki Tano, Takeshi Masuura, Takamichi Miyamoto, Jun Shirako, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara, "Multigrain Parallelization of Restricted C Programs　in SMP Execution Mode of a Multicore for Consumer Electronics", Embedded Systems Symposium 2007 （ESS 2007), Oct. 2007. (With Review) (pdf)
  2. Masayoshi Mase, "Automatic Parallelizing Compiler Technology for Consumer Electronics", STARC Symposium 2007, Sep. 2007. (Without Review) (pdf)

　

Poster Presentation

  1. "Parallelizing Compiler Cooperative Multicore Technology -- Easy-to-use, High performance, Low power consumption, High-value added Multicore Prosessor -- ", The 5th Technology Link in W.T.L.O - For International Research Center in Collaboration of Industry and Academia, Oct. 2007.
  2. M. Mase, D. Baba, H. Nagayama, H. Tano, T. Masuura, T. Miyamoto, J. Shirako, H. Nakano, K. Kimura, H. Kasahara
    , "Multigrain Parallelization of Restricted C Programs on SMP Servers and Low Power Multicores", The 20th International Workshop on Languages and Compilers for Parallel Computing (LCPC2007), Oct. 2007. (pdf)
  3. Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, "Power-Aware Compiler Controllable Heterogeneous Chip Multiprocessor", The Sixteenth International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), Brasov, Romania, Sep. 2007.

　

Press (96)

Press Concerning RP1 (33)

 Articles in Newspapers

  1. Nihon Keizai Shimbun (News Paper), "Parallel Processing Software for Consumer Electronics Development by Waseda, Hitachi, etc.", Jun. 01. 2007.
  2. Nikkan Kogyo Shimbun (News Paper), "Parallel Processing on Multicore LSI", Jun. 01. 2007.
  3. Nikkei Sangyo Shimbun (News Paper), "Waseda Univ. etc. Developed Multicore Software", Jun. 01. 2007.
  4. Dempa Shimbun (News Paper), "Waseda/Hitachi/Renesas Developed Multicore Technology to Reduce Software Development Period", Jun. 01. 2007.
  5. Demkei Shimbun (News Paper), "Development of Multicore Technology for Efficient Development of Consumer Electronics", Jun. 04. 2007.
  6. Kagaku Kogyo Shimbun (News Paper), "Development of Consumer Electronics Software : High Speed Processing by Multicore Technology", Jun. 04. 2007.
  7. Nihon Joho Sangyo Shimbun (News Paper), "Waseda Univ. etc. Developed a New Multicore Technology for Quick Software Development of Consumer Electronics", Jun. 11. 2007.
  8. Dempa Shimbun (News Paper), "Development of Multicore Technology : Shorten development period of consumer electronics", Jun. 14. 2007.

 Articles in Journals, etc.

  1. Waseda University CAMPUS NOW, Vol. 173, "Development of Multicore Technology to Reduce Development Period of Consumer Electronics", Jul. 06. 2007.
  2. EE Times Japan　E-mail News Letter (no.98), "Parallelizing Compiler Technology for Multicores : Development by Waseda, Hitachi, Renesas", Jun. 13. 2007.

 Web News

  1. EE TIMES Japan , "Parallelizing Compiler Technology for Multicores : Development by Waseda, Hitachi, Renesas", Jun. 08. 2007.
  2. IPNEXT, "Waseda Univ. and Hitachi etc. Developed Multicore Technology to Reduce Development Period of Consumer Electronics", Jun. 03. 2007.
  3. Kankyoubu.com, "Waseda Univ. and Hitachi etc. Developed Multicore Technology to Reduce Development Period of Consumer Electronics", Jun. 03. 2007.
  4. NIKKEI NET IT PLUS, "Waseda Univ. etc. Developed Multicore Software : Enhancing Performance of Digital Consumer Electronics", Jun. 01. 2007.
  5. IBTimes, "Waseda Univ. and Hitachi etc. Developed Multicore Technology to Reduce Development Period of Consumer Electronics", Jun. 01. 2007.
  6. CMSNAVI, "Waseda Univ. and Hitachi etc. Developed Multicore Technology to Reduce Development Period of Consumer Electronics", Jun. 01. 2007.
  7. Electronic Journal, "Waseda Univ., Hitachi, Renesas Developed Multicore Technology by Automatic Parallelizing Technology", Jun. 01. 2007.
  8. Semiconductor Japan Net, "Waseda Univ. etc. Co-developed Multicore Technology to Reduce Development Period of Consumer Electronics", Jun. 01. 2007.
  9. Nippon R&D Community, "Waseda Univ., Hitachi, Renesas Technology Developed Multicore Technology to Shorten Development Period of Consumer Electronics", Jun. 01. 2007.
  10. Kabuka Zairyo, "Hitachi etc. Established Technology to Reduce Development Period of Multicore LSI", Jun. 01. 2007.
  11. asahi.com, "Hitachi etc. Established Technology to Reduce Development Period of Multicore LSI", Jun. 01. 2007.
  12. Yahoo Japan News（Nikkan Kogyo Shimbun）, "Hitachi etc. Established Technology to Reduce Development Period of Multicore LSI", Jun. 01. 2007.
  13. Micro Technology Business, "Hitachi etc. Developed Multicore Technology to Reduce Development Period of Consumer Electronics", Jun. 01. 2007.
  14. News about Semiconductor and Car Electronics, "Hitachi, Waseda Univ., Renesas Show off Power of Parallelizing Compiler Technology for Multicore SoC", Jun. 01. 2007.
  15. NIKKEI NET, "Waseda Univ., Hitachi, Renesas Technology Developed Multicore Technology to Shorten Development Period of Consumer Electronics"　Headline , May. 31. 2007.
  16. Nikkei Electronics Tech On, "Hitachi, Waseda Univ., Renesas Show off Power of Parallelizing Compiler Technology for Multicore SoC", Jun. 01. 2007.
  17. Nikkei Electronics Tech On, "Hitachi, Waseda Univ., Renesas Show off Power of Parallelizing Compiler Technology for Multicore SoC", Jun. 01. 2007.
  18. JCN Network, "Waseda Univ., Hitachi, Renesas Technology Developed Multicore Technology to Shorten Development Period of Consumer Electronics", May. 31. 2007.
  19. Infoseek Money, "Waseda Univ., Hitachi, Renesas Technology Developed Multicore Technology to Shorten Development Period of Consumer Electronics", May. 31. 2007.
  20. Matsui Securities, "Waseda Univ., Hitachi, Renesas Technology Developed Multicore Technology to Shorten Development Period of Consumer Electronics", May. 31. 2007 

 Press Release

  1. Waseda University Press Release, "Waseda Univ., Hitachi, Renesas Technology Developed Multicore Technology to Shorten Development Period of Consumer Electronics", May. 31. 2007.
  2. Hitachi Press Release, "Waseda Univ., Hitachi, Renesas Technology Developed Multicore Technology to Shorten Development Period of Consumer Electronics", May. 31. 2007.
  3. Renesastechnology Press Release, "Waseda Univ., Hitachi, Renesas Technology Developed Multicore Technology to Shorten Development Period of Consumer Electronics", May. 31. 2007.

Press Concerning SGI Altix450 (17)

 Articles in Newspapers

  1. Nikkei Sangyo Shimbun (News Paper), "SGI Japan Installed Compact Server to Waseda Univ.", Jan. 07. 2008.
  2. Dempa Shimbun (News Paper), "SGI Japan Installed 3 Mid Range Servers to Kasahara Lab, Waseda Univ. for Parallelizing Compiler Research", Dec. 27. 2007.
  3. Dempa Shimbun Data Communication (News Paper), "Midrange Server : Waseda kasahara Lab", Feb. 18. 2008.

 Web News

  1. SGI e-News No.94, "SGI Japan Installed Mid Range Servers "Altix 450" to Kasahara Lab, Waseda Univ. Introduction of Efforts and Goal of  Research and Development", Feb. 27. 2008.
  2. SGI e-News No.91, "SGI Japan Installed Mid Range Servers "Altix 450" to Kasahara Lab, Waseda Univ. Contribution to Research Theme 'Improvement of Computer's Processing Speed and Reduction of Software Development Period'", Jan. 16. 2008.
  3. IT media　Enterprize, "Deskside Super Computer Supports Development of Automatic Parallelizing Compilers for Multicore", Jan. 15. 2008.
  4. livedoor News, "Deskside Super Computer Supports Development of Automatic Parallelizing Compilers for Multicore", Jan. 15. 2008.
  5. NEWS@nifty, "Deskside Super Computer Supports Development of Automatic Parallelizing Compilers for Multicore", Jan. 15. 2008.
  6. YahooNews, "Deskside Super Computer Supports Development of Automatic Parallelizing Compilers for Multicore", Jan. 15. 2008.
  7. infoseekNews, "Deskside Super Computer Supports Development of Automatic Parallelizing Compilers for Multicore", Jan. 15. 2008.
  8. Excite News Press Release, "SGI Japan Installed Mid Range Servers "Altix 450" to Kasahara Lab, Waseda Univ.", Dec. 27. 2007.
  9. YahooNews, "SGI Japan Installed Mid Range Servers "Altix 450" to Kasahara Lab, Waseda Univ.", Dec. 27. 2007.
  10. webBCN, "SGI Japan Installed Mid Range Servers "Altix 450" to Kasahara Lab, Waseda Univ.", Dec. 27. 2007.
  11. asahi.com, "SGI Japan Installed Mid Range Servers "Altix 450" to Kasahara Lab, Waseda Univ.", Dec. 27. 2007.
  12. Security Online News, "SGI Japan Installed Mid Range Servers "Altix 450" to Kasahara Lab, Waseda Univ. : Small-Footprint, Power-Saving, and High-Performance Deskside Computer Reduces Software Development Period", Dec. 25. 2007.
    　

 Press Release

  1. SGI Japan Press Release, "Parallelizing Compiler Research for Multicore Processor. SGI Japan Installed Mid Range Servers "Altix 450" to Kasahara Lab, Waseda Univ. : Small-Footprint, Power-Saving, and High-Performance Deskside Computer Reduce Software Development Period", Dec. 25. 2007.
  2. Waseda University Press Release, "Parallelizing Compiler Research for Multicore Processor. SGI Japan Installed Mid Range Servers "Altix 450" to Kasahara Lab, Waseda Univ. : Small-Footprint, Power-Saving, and High-Performance Deskside Computer Reduce Software Development Period", Dec. 25. 2007.

Press Concerning RP2 (35)

 Articles in Newspapers

  1. Nikkei Sangyo Shimbun (News Paper), "80% Cousumed Power Reduction in Digital Consumer Electronics LSI", Feb. 04. 2008.
  2. Nikkan Kogyo Shimbun (News Paper), "Parallelizing Compiler Technology for Multicores : Development by Waseda, Hitachi, Renesas", Feb. 04. 2008.
  3. Dempa Shimbun (News Paper), "Waseda, Hitachi, Renesas Development of Low Power Consumption Technology for Multicore LSI", Feb. 04. 2008.
  4. Denki Shimbun (News Paper), "Development of LSI Consumed Power Reduction Technology for Consumer Electronics Waseda, Hitachi, etc.", Feb. 04. 2008.
  5. Kagaku Kogyo Shimbun (News Paper), "Multicore LSI Reduction of Consumed Power by Compiler Collaboration", Feb. 05. 2008.

 Articles in Journals, etc.

  1. Nikkei Electronics, No.969 (Jan. 14, 2008), "High Performance Digital : Coping with Consumed Power", Jan. 14. 2008.

 Web News

  1. EE TIMES Japan , "【ISSCC 2008】Large Reduction of Consumed Power with Compiler Collaboration", Feb. 06. 2008.
  2. asahi.com, "Waseda, Hitachi, Renesas Developed Low Power Consumption Technology for Consumer Electronics", Feb. 04. 2008.
  3. Nikkei Navi 2008, "Information Processing Software Renesas etc. Reduced 80% consumed Power", Feb. 04. 2008.
  4. Japan Edition Semiconductor International , "Low Power Consumption Technology of Multicore LSI", Mar. 2008
  5. The Unix Guardian, "Rock and Tukwila Are the Stars of ISSCC This Week ", Feb. 07. 2008.
  6. Semiconductor Japan Net, "Waseda etc. Developed Low Power Consumption Technology of Multicore LSI", Feb. 07. 2008.
  7. Mycomi Journal, "ISSCC 2008 : Tilera, Tile 64 Compared with Renesas Technology's 8 core chip", Feb. 06. 2008.
  8. ELISNET, "Development of Low Power Consumption Technology for Multicore LSI for Consumption Electronics", Feb. 05. 2008.
  9. Nikkei ElectronicsTech On, "[ISSCC] To a New ERA : Compiler Considers Consumed Power Waseda, Hitachi, Renesas Developed the Technology", Feb. 05. 2008.
  10. Mycomi Journal, "Renesas etc Developed Low Power Consumption Technology of Multicore LSI by Parallelizing Compiler", Feb. 05. 2008.
  11. media jam, "Renesas etc Developed Low Power Consumption Technology of Multicore LSI by Parallelizing Compiler", Feb. 05. 2008.
  12. Micro Technology Business, "Hitachi, Renesas, Waseda Univ. etc Developed Low Power Consumption Technology of Multicore LSI", Feb. 05. 2008.
  13. Nikkan Kogyo Shimbun　Business Line, "Waseda, Hitachi, Renesas Developed Low Power Consumption Technology for Consumer Electronics", Feb. 04. 2008.
  14. Yahoo News, "Waseda, Hitachi, Renesas Developed Low Power Consumption Technology for Consumer Electronics", Feb. 04. 2008.
  15. EDA Express, "Renesas, Hitachi, Waseda Univ. Co-developed Low Power Consumption Technology for Multicore LSI  by Parallelizing Compiler", Feb. 04. 2008.
  16. EDA News, "Renesas, Hitachi, Waseda Univ. Co-developed Low Power Consumption Technology for Multicore LSI  by Parallelizing Compiler", Feb. 04. 2008.
  17. NIKKEI NET, "Renesas etc. 80% Cousumed Power Reduction in Digital Consumer Electronics LSI (Feb. 4, 2008)", Feb. 04. 2008.
  18. Impress Watch, "【ISSCC 2008 Previous Report】 Low Power Consumption Processor", Feb. 04. 2008.
  19. Yahoo News, "【ISSCC 2008 Previous Report】 Low Power Consumption Processor", Feb. 04. 2008.
  20. Yahoo Game, "【ISSCC 2008 Previous Report】 Low Power Consumption Processor", Feb. 04. 2008.
  21. infoseek News, "【ISSCC 2008 Previous Report】 Low Power Consumption Processor", Feb. 04. 2008.
  22. Denshi Journal, "Waseda Univ., Hitachi, Renesas Developed Low Power Consumption Technology for Multicore LSI for Consumer Electronics", Feb. 04. 2008.
  23. Kabuka Zairyo, "Waseda Univ., Hitachi, Renesas Developed Low Power Consumption Technology for Multicore LSI for Consumer Electronics", Feb. 04. 2008.
  24. Waseda Univ. HP, "Waseda Univ., Hitachi, Renesas Developed Low Power Consumption Technology for Multicore LSI for Consumer Electronics", Feb. 04. 2008.
  25. Faculty of Science and Engineering, Waseda Univ. HP, "Waseda, Hitachi, Renesas Developed Low Power Consumption Technology for Consumer Electronics (Prof. Hironori Kasahara, Dept. of Computer Science)", Feb. 04. 2008.
  26. Mycomi Journal, "ISSCC 2008 Preview : Microprocessor Session", Jan. 20. 2008.
    　

 Press Release

  1. Waseda University Press Release, "Development of Low Power Consumption Technology of Multicore LSI for Consumer Electronics", Feb. 04. 2007.
  2. Hitachi Press Release, "Development of Low Power Consumption Technology of Multicore LSI for Consumer Electronics", Feb. 04. 2007. 
  3. Renesastechnology Press Release, "Development of Low Power Consumption Technology of Multicore LSI for Consumer Electronics", Feb. 04. 2007.
    　

Other (11)

 Articles in Newspapers

  1. Asahi Shimbun (News Paper), "IT Apparatus : Pressing need for saving energy", Feb. 19. 2008.
  2. Nikkei Sangyo Shimbun (News Paper), "Waseda University Hironori Kasahara Laboratory : A New Value Creation by Combining Research and Needs for Multicore Technology", Sep. 11. 2007. 

 TV Program

  1. TBS　BSi　TV Program, "Waseda University: Innovation of University Management in the 125th Anniversary", Global Navi, Jul. 28. 2007.

 Articles in Journals, etc.

  1. MEXT Next Generation Supecomputer Concept WG, "Report on  Next Generation Supercomputer Concept Design Evaluation", Jun. 12. 2007.
  2. NEDO Electronics and Information Technology Roadmap, "NEDO Roadmap Committee Report", May. 31. 2007.
  3. RENESAS Edge Vol.17 pp.04, "Special Issue on Advanced Embedded Microprocessors", Apr. 01. 2007.
  4. RENESAS Edge Vol.17 pp.04, "SH-4A Multicore", Apr. 01. 2007.
  5. HITACHI　2007Spring pp.13-15, "Microprocessor", Apr. 01. 2007.

 Web News

  1. asahi.com "Cover Story: IT warming", Mar. 05. 2008.
  2. Faculty of Science and Engineering, Waseda Univ. HP, News & Events, "Announcement of Waseda Univ. 125 th & Faculty of Science and Engineering 100th Anniversary Symposium "Innovative Information, Electronics, and Optical technology"", Sep. 14. 2007.
  3. Waseda Univ. HP, News & Events, "Announcement of Waseda Univ. 125 th & Faculty of Science and Engineering 100th Anniversary Symposium "Innovative Information, Electronics, and Optical technology"", Sep. 11. 2007.

　

Awards

  1. Masayoshi Mase, "STARC (Semiconductor Technology Academic Research Center) Symposium 2007 Poster Award", Sep. 2007.

　

Patents

　Registration of patent

  1. "MULTIPROCESSOR SYSTEM AND MULTIGRAIN PARALLELIZING COMPILER", 4082706(JP Patent), Feb.22.2008.

　Published applications for patent

  1. "GLOBAL COMPILER FOR CONTROLLING HETEROGENEOUS MULTIPROCESSOR", 1881405(EP Publication), Jan.23.2008. [Registration of patent:1881405(EP Patent), Jul.25.2018.]
  2. "GLOBAL COMPILER FOR CONTROLLING HETEROGENEOUS MULTIPROCESSOR", 1881405(DE Publication), Jan.23.2008. [Registration of patent:602007055494.2(DE Patent), Jul.25.2018.]
  3. "GLOBAL COMPILER FOR CONTROLLING HETEROGENEOUS MULTIPROCESSOR", 1881405(FR Publication), Jan.23.2008. [Registration of patent:1881405(FR Patent), Jul.25.2018.]
  4. "GLOBAL COMPILER FOR CONTROLLING HETEROGENEOUS MULTIPROCESSOR", 1881405(GB Publication), Jan.23.2008. [Registration of patent:1881405(GB Patent), Jul.25.2018.]
  5. "MULTIPROCESSOR SYSTEM AND MULTIGRAIN PARALLELIZING COMPILER", 1870792(EP Publication), Dec.26.2007.
  6. "MEHTOD FOR CONTROLLING HETEROGENEOUS MULTIPROCESSOR AND MULTIGRAIN PARALLELIZING COMPILER", 2007-328415(JP Publication), Dec.20.2007. [Registration of patent:4936517(JP Patent), Mar.02.2012.]
  7. "GLOBAL COMPILER FOR CONTROLLING HETEROGENEOUS MULTIPROCESSOR", 2007-328416(JP Publication), Dec.20.2007. [Registration of patent:4784827(JP Patent), Jul.22.2011.]
  8. "GLOBAL COMPILER FOR HETEROGENEOUS MULTIPROCESSOR", CN101086710A(CN Publication), Dec.12.2007.
  9. "GLOBAL COMPILER FOR HETEROGENEOUS MULTIPROCESSOR", 10-2007-0116712(KR Publication), Dec.11.2007. [Registration of patent:10-0878917(KR Patent), Jan.08.2009.]
  10. "MEHTOD FOR CONTROLLING HETEROGENEOUS MULTIPROCESSOR AND MULTIGRAIN PARALLELIZING COMPILER", 2007/0283358(US Publication), Dec.06.2007. [Registration of patent:8250548(US Patent), Aug.21.2012.]
  11. "GLOBAL COMPILER FOR CONTROLLING HETEROGENEOUS MULTIPROCESSOR", 2007/0283337(US Publication), Dec.06.2007. [Registration of patent:8051412(US Patent), Nov.01.2011.]
  12. "MULTIPROCESSOR SYSTEM AND MULTIGRAIN PARALLELIZING COMPILER", 2007-305148(JP Publication), Nov.22.2007.
  13. "MULTIPROCESSOR SYSTEM AND MULTIGRAIN PARALLELIZING COMPILER", 2007/255929(US Publication), Nov.01.2007. [Registration of patent:7895453(US Patent), Feb.22.2011.]
  14. "MULTIPROCESSOR SYSTEM AND MULTIGRAIN PARALLELIZING COMPILER", 101019084(CN Publication), Aug.15.2007. [Registration of patent:ZL200680000666.0(CN Patent), Jul.15.2009.]
  15. "MULTIPROCESSOR SYSTEM AND COMPUTER READABLE MEDIUM RECORDING MULTIGRAIN PARALLELIZING COMPILER", 10-2007-0061795(KR Publication), Jun.14.2007. [Registration of patent:10-0861631(KR Patent), Sep.26.2008.]