2005

Papers

  1. Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara, "Parallelizing Compilation Scheme for Reduction of Power Consumption of Chip Multiprocessors", Proc. of 12th Workshop on Compilers for Parallel Computers　(CPC 2006), Jan. 2006. (pdf)

  2. H. Kasahara, K. Kimura, "1.Multicores Emerge as Next Generation Microprocessors", IPSJ MAGAZINE, Vol.47, No.1, pp.10-16, Jan. 2006.

  3. H. Kasahara, K. Kimura, "2.Programing for Multicore Systems", IPSJ MAGAZINE, Vol.47, No.1, pp.17-23, Jan. 2006.

  4. Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara, "Compiler Control Power Saving Scheme for Multi Core Processors", Proc. of The 18th International Workshop on Languages and Compilers for Parallel Computing (LCPC2005), Oct. 2005. (pdf) 

  5. Kazuhisa Ishizaka,Takamichi Miyamoto, Jun Shirako, Motoki Obata, Keiji Kimura, Hironori Kasahara, "Performance of OSCAR Multigrain Parallelizing Compiler on SMP Servers", Lecture Notes in Computer Science , Vol. 3602, pp.319, 2005

  6. Takeshi Kodaka, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara, "Parallel Processing of MPEG2 Encoding on a Chip Multiprocessor Architecture", Trans. of IPSJ, Vol. 46, No. 9,　pp.2311-2325, Sep. 2005.

　

Invited talks

  1. Hironori Kasahara, "Parallelizing Compiler Cooperated Low Power High Effective Performance Multi-core Processors", 158th IPSJ Special Interest Group on Computer Architecture (SHINING 2006), Jan. 2006.(pdf)

  2. H. Kasahara, “Road map of the computer area”, NEDO Electronics and Information Technology Road map Accomplishment Report Symposium, Tokyo, May. 2005. (pdf) ,

  3. H. Kasahara, “Compiler technology for built-in multi-core processor”, ARM Seminar 2005, Tokyo, Jun. 2005. (pdf)

  4. H. Kasahara, "Advanced High-Performance Computer", Lecture on 'Advanced technology and intellectual property in Nano and IT', Program for cultivation of people in new fields of study 'Upskilling program for Nano, IT, Bio - Intellectual Property Management Strategy', Promotion Budget for Science and Technology from MEXT, Tokyo, May. 2005.

　

Technical Reports

  1. Hironori Kasahara, "Parallelizing Compiler Cooperated Low Power High Effective Performance Multi-core Processors", 158th IPSJ Special Interest Group on Computer Architecture (SHINING 2006), Jan. 2006. (pdf)

  2. Hiroaki Shikano, Yuki Suzuki, Yasutaka Wada, Jun Shirako, Keiji Kimura, Hironori Kasahara, "Preliminary Evaluation of Heterogeneous Chip Multi-Processor with MP3 Audio Encoder", 158th IPSJ Special Interest Group on Computer Architecture (SHINING 2006), Jan. 2006. (To be appeared)

  3. Yasutaka Wada, Naoto Oshiyama, Yuki Suzuki, Yosuke Naito, Jun Shirako, Keiji Kimura, Hironori Kasahara, "A Static Scheduling Scheme for Coarse Grain Tasks on a Heterogeneous Chip Multi Processor", 158th IPSJ Special Interest Group on Computer Architecture (SHINING 2006), Jan. 2006.(To be appeared)

  4. Hiforumi Nakano, Shoichiro Asano, Yosuke Naito, Takumi Nito, Tomohiro Tagawa, Takaumichi Miyamoto, Takeshi Kodaka, Keiji Kimura, Hironori Kasanara, "Data Localization on a Multicore Processor", Technical Report of IPSJ, 2005-ARC-165-10, pp.51-56, Dec. 2005. (pdf)

  5. Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara, " Compiler Control Power Saving Scheme for Homogeneous Multiprocessor", Technical Report of IPSJ, 2005-ARC-164-10, pp.55-60, Aug. 2005, 2005 (pdf)

　

Symosium

  1. Hironori Kasahara, Keiji Kimura, Hirofumi Nakano, Jun Shirako, Takamichi Miyamoto, Yasutaka Wada, "Parallelizing Compiler Cooperative Chip Multiprocessor Technology", STARC Symposium 2005, Sep. 2005. (Without Review)

Articles in Newspapers

  1. Yomiuri Shimbun, "Is There a Limit of Speedup of Supercomputers? " Hot Science Nattoku Kagaku, Jan. 28. 2006.

Articles

  1. PC-Webzine, Vol.165, pp.100, - Site of Academic/Research Field - "Learning about Theory of Opinion Reader", Nov. 2005.
  2. Chuokoron-Shinsha, Advanced Research from Laboratories, Energetic Research Activities in Waseda University, pp.28-37, Chapter 1 Closing Up of the Forefront of Science and Technology "2. Overwhelmed out the World by Parallelizing Compiler and Multicore Processor", Sep. 10. 2005.
  3. Nikkei BP Mook, School of Science and Engineering, Waseda University 2006-2007, pp. 39, "Face-to-face communication! This is distinctive advantage of Tokyo.", Dec. 28. 2005.

Web News

  1. NEDO, "Easily Understandable! 'Electronics and IT Field: Advanced Parallelizing Compiler Project'", 2005

  2. NEDO Press Release, “NEDO Adds Four New Themes to ‘Semiconductor Application Chip Project’ ”, Jun. 30. 2005

  3. Waseda University Liaison Office Press Release "Adopted for Semiconductor Application Chip Project at NEDO 'Research and Development of Real-Time Multi-Core Technology for Information Appliances' Waseda University, Hitachi Ltd. and Renesas Technology Corp. (Project leader / Prof. Hironori Kasahara) "  Jul. 05. 2005

  4. The 4th Conference for the Promotion of Collaboration among Business, Academia, and Government, Special Lecture by Dr. Kenji Takeda (RIKEN Executive Directors, Former Hitachi General Manager of Research Alliance in Headquarter of Research and Developnent), "'Japanese Hinomaru Processor' Cooperation between Hitachi and Waseda University (NEDO Matching Fund), Research of Advanced Heterogeneous Multiprocessor", Jun. 25. 2005.