2006

Papers

  1. Y. Yoshida, T. Kamei, K. Hayase, S. Shibahara, O. Nishii, T. Hattori, A. Hasegawa, M. Takada1, N. Irie1, K. Uchiyama, T. Odaka, K. Takada, K. Kimura, H. Kasahara, "A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption", Proc. of 2007 IEEE International Solid-State Circuits Conference(ISSCC2007), Feb. 2007.
  2. Jun Shirako, Munehiro Yoshida, Naoto Oshiyama, Yasutaka Wada, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara, "Compiler Control Power Saving Scheme for Multicore Processors", Trans. of IPSJ on Computing Systems, Vol. 47(ACS15), 2006 .(pdf)
  3. Jun Shirako, Munehiro Yoshida, Naoto Oshiyama, Yasutaka Wada, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara, "Performance Evaluation of Compiler Controlled Power Saving Scheme", Proc. of 20th ACM International Conference on Supercomputing Workshop on Advanced Low Power Systems(ALPS2006), Jul. 2006. (pdf)
  4. Hiroaki Shikano, Yuki Suzuki, Yasutaka Wada, Jun Shirako, Keiji Kimura, Hironori Kasahara, "Performance Evaluation of Heterogeneous Chip Multi-Processor with MP3 Audio Encoder", Proc. of IEEE Symposium on Low-Power and High Speed Chips (COOL Chips IX), pp.349-363, Apr. 2006. (pdf)

Technical Reports

  1. Tsuyoshi Miura, Tomohiro Tagawa, Yusuke Muramatsu, Akinori Ikemi, Masahiro Nakagawa, Hirofumi Nakano, Jun Shirako, Keiji Kimura, Hironori Kasahara, "A Local Memory Management Scheme in Multigrain Parallelizing Compiler", Technical Report of IPSJ, 2007-ARC-172/HPC-109-11, Mar. 2007. (pdf)
  2. Takamichi Miyamoto, Saori Asaka, Nobuhito Kamakura, Hiromasa Yamauchi, Masayoshi Mase, Jun Shirako, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara, "Automatic Parallelization for Multimedia Applications on Multicore Processors", Technical Report of IPSJ, 2007-ARC-171-13, Jan. 2007. (pdf)
  3. Jun Shirako, Tomohiro Tagawa, Tsuyoshi Miura, Takamichi Miyamoto, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara, "Performance of OSCAR Multigrain Parallelizing Compiler on SMP Servers and Embedded Multicore", Technical Report of IPSJ, 2006-ARC-170-02 (DesignGaia2006), Nov. 2006. (pdf)
  4. Masayoshi Mase, Daisuke Baba, Harumi Nagayama, Hiroaki Tano, Takeshi Masuura,　Koji Fukatsu, Takamichi Miyamoto, Jun Shirako, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara, "Automatic Parallelization of Restricted C Progurams in OSCAR Compiler", Technical Report of IPSJ, 2006-ARC-170-01 (DesignGaia2006), Nov. 2006. (pdf)
  5. Hirofumi Nakano, Takumi Nito, Takanori Maruyama, Masahiro Nakagawa, Yuki Suzuki, Yousuke Naito,Takamichi Miyamoto, Yasutaka Wada, Keiji Kimura, Hironori Kasahara,"Local Memory Management on OSCAR Multicore'', Technical Report of IPSJ, 2006-ARC-169-28, pp. 163-168, Aug. 2006(pdf)
  6. Fumiyo Takano, Yoshitaka Maekawa, Hironori Kasahara, Seinosuke Narita, "Parallelization of Multi-Path Concurrent Search for Iterative Deepening using Proof and Disproof Numbers", Technical Report of IPSJ, 2006-HPC-103-17/ (SWoPP2006), Aug. 2006.(pdf)

Invited Talks
  1. Hironori Kasahara, "Multi-core Parallelizing Compiler for Low Power High Performance Computing", University of Illinois at Urbana-Champaign, Hosted by Prof. David Padua, USA, Oct. 2006.(pdf)
  2. Hironori Kasahara, "Advanced Computer Architecture: METI/NEDO Multicore-processor Technology for Real-time Consumer Electronics Project", Tokyo Electric Power Company EWE Seminor 2006, Tokyo, Oct. 2006.
  3. Hironori Kasahara, "Advanced Multi-core Compiler and Its Parallelization and Power Reduction Performance", ARM Seminar 2006, Tokyo, Oct. 2006. ,
  4. Masayoshi Mase, Keiji Kimura, Hironori Kasahara, "C Language Support in OSCAR Multigrain Parallelizing Compiler using CoSy", ACE 2nd CoSy Community Gathering, Amsterdam, Netherlands, Oct. 2006.(pdf)  
  5. Hironori Kasahara, "OSCAR Multigrain Parallelizing Compiler foor Multicore Architectures", Workshop on Software Challenges for Multicore Architectures, Tshinghua Univ. Beijing, China, Sep. 2006 (pdf)
  6. Guang R. Gao, Kasahara Hironori, Vivek Sarkar, Skevos Evripidou, Murphy Brian , "Software Challenges in Multi-Core Chip Era (Panel Discussion)", Workshop on Software Challenges for Multicore Architectures, Tshinghua Univ. Beijing, China, Sep. 2006. (pdf)
  7. Hironori Kasahara, "Multicores for Consumer Electronics and Parallelizing Compilers", JEITA SIG. on Microprocessor, Tokyo, Aug. 2006.
  8. Hironori Kasahara, "The Latest Trend of Parallelizing Compiler", IBM Japan Forum on Pioneering Scientific Computing, Fukuoka, Aug. 2006.
  9. Hironori Kasahara, "Trial s of Collaboration among Business, Academia and Governmentand Human Resource Development for Creation of Innovations(Panel on the Promotion of Collaboration among Business, Academia and Government and Human Resource Development for Creation of Innovations)", 5th Conference for the Promotion of Collaboration Among Business, Academia, and Government (Section Meeting), Kyoto, Jun. 2006. (pdf)
  10. Hironori Kasahara, "Latest Trends of Multi-CPU Architectures and Parallelizing Compilers: Application for Consumer Electronics", Sony Technology seminar, Tokyo, May. 2006.

Symposium

  1. Hironori Kasahara, Keiji Kimura, Jun Shirako, Yasutaka Wada, Hirofumi Nakano, Takamichi Miyamoto, "Parallelizing Compiler Cooperative Chip Multiprocessor Technology", STARC Symposium 2006, Sep. 2006. (Without Review) (pdf)

  2. Jun Shirako, Munehiro Yoshida, Naoto Oshiyama, Yasutaka Wada, Hirohumi Nakano, Hiroaki Shikano Keiji Kimura, Hironori Kasahara "Compiler Control Power Saving Scheme for Multicore Processor", Symposium on Advanced Computing Systems and Infrastructures (sacsis-2006), May. 2006. (With Review) (pdf)

Articles in Newspapers

  1. Asahi Shimbun, "Toward the Fastest Supercomputers", Nov. 24. 2006.
  2. Asahi Shimbun, "Science & Technology Research Contest JSEC An Important Chance for High School Students to Know the Fun of Research and Development", Jun. 21. 2006.

Articles

  1. Nikkei Microdevices Special Edition 2007, "Introduction of Kasahara Research Group: Compiler Cooperated Chip Multiprocessor", Mar. 2007.
  2. IBM High Performance Computing Case Introduction, "Creation of World Best Parallelizing Compiler: Toward to the Era of Multi-core Everywhere in the 21th Century", Sep. 21. 2006. 
  3. MEXT the 10th Convention for Coordinators of Collaboration of Business, Academia and Government, "A special Theme Case: Strengthening International Competitiveness: Real-time Multi-core for Consumer Electronics", Sep. 16. 2006.
  4. Brochure about NEDO Electronic & Information Technology Development Dept. pp.20-21, "II. Outline of Projects - The fields of Semiconductor Technology - (2) Semiconductor Application Chip Project (Field of Information Appliances)", Sep. 2006
  5. Brochure about NEDO Electronic & Information Technology Development Dept. pp.60, "IV. Outline of Completed Projects (19) Research and Development of Advanced Parallelizing Compiler", Sep. 2006

Web News

  1. MYCOM Journal, "ARM Forum 2006- Cortex Family and Compilers for Multi-core", Oct. 24. 2006. 
  2. MYCOM Journal, "Arm Forum 2006 - Potential of Multi-core Compilers", Oct. 24. 2006.
  3. PC Watch, "Fall Microprocessor Forum Report: Renesas Developed SuperH Core for Multi-core", Oct. 13. 2006.
  4. Digital New Deal, "Viewpoint and Issues in the 5th Conference on Collaboration of Industry, Academia and Government", Jun. 2006

Award

  1. Jun Shirako, "IPSJ SACSIS Young Researcher Award ", May. 2006.
  2. Jun Shirako, "IEEE Computer Society Japan Chapter Award", May. 2006.
  3. Masayoshi Mase, "Design Gaia 2006 Poster Award", Nov. 2006. 
  4. Hiroaki Shikano, "IPSJ Yamashita SIG Research Award", Mar. 2007.

Patents

　Published applications for patent

  1. "MULTIPROCESSOR SYSTEM AND MULTIGRAIN PARALLELIZING COMPILER", 2006-293768(JP Publication), Oct.26.2006. [Registration of patent:4082706(JP Patent), Feb.22.2008.]
  2. "MULTIPROCESSOR SYSTEM AND MULTIGRAIN PARALLELIZING COMPILER", 06/109887(WO Publication), Oct.19.2006.