Professor
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Hironori KASAHARA

 E-mail: kasahara_at_waseda_dot_jp (_at_: @, _dot_: .)
Department of Computer Science, Waseda University
Advanced Multicore Processor Research Institute, Waseda University
Activities in Societies and Government
List of Papers, Awards and Patents
News
IEEE Computer Society President Position Statement & Biography.
 Election Information, voting(Aug.4 - Oct.6,2014)

Office:

55N-505A,505B,506A,507A
Green Computing Systems R&D Center 501-503, 706

Brief personal history:

B.S.(1980,Waseda), M.S.(1982,Waseda),
Dr. Eng. (1985,Waseda). Res. Assoc.(1983,Waseda),
Assist. Prof.(1986. Waseda), Assoc. Prof.(1988,Waseda),
Prof.(1997, Waseda).

Visiting Scholar (1985. Univ. California at Berkeley)
Visiting Research Scholar(1989-1990. Center for Supercomputing R & D, Univ. of Illinois at Urbana-Champaign)
IEEE Computer Society Board of Governor (2009-)

Young Author Prize: IFAC Triennial World Congress(1987)
IPSJ Sakai Memorial Special Award (1997)
STARC (Semiconductor Technology Academic Research Center) Industry-Academia Cooperative Research Award (2005)
2008 LSI Of The Year The Second Prize (2008)
IEEE Computer Society Golden Core Member (2010)

Visiting Prof.(2010.9.1 - 2011.8.31. Egypt Japan University for Science and Technology (E-JUST) )

Prizes for Science and Technology (Research), The Commendation for Science and Technology by the Minister of Education, Culture, Sports, Science and Technology (2014)

Key words:

Automatic Parallelizing Compiler, Supercomputing, Multicore, Manycore, Green Computing, Scheduling Algorithms, Multi-platform API, Parallel applications (Embedded Systems, Medical image processing, Mobile phones, Automobiles, Electronic Circuit Simulation, Natural disaster simulation, etc)

Research:

  1. Next generation chip multiprocessor architectures for mobile phones, games, Digital TVs, DVDs, car navigation systems to supercomputers.
  2. Automatic multigrain parallelizing compilers with memory optimization and data transfer optimizaton/
  3. Minimum execution time multiprocessor scheduling algorithms considering minimization of data transfer overhead with data decomposition and assignment.
  4. User friendly application specific parallelizing compilers for electronic circuit simulation, mobile phones, games, car navigation systems, cars, digital TVs, and so on.

Please see Research Topics in homepage of KASAHARA Lab. for more details.

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OSCAR : Optimally Scheduled Advanced Multiprocessor