Yanqing Liu

Yanqing Liu

Computer Architecture & Security

Ph.D. Student · School of Fundamental Science and Engineering
Waseda University, Tokyo

Education

Academic Background

2026.04 — Present

Ph.D. in Computer ScienceIn Progress

Waseda University, Tokyo, Japan

School of Fundamental Science and Engineering
Research focus: Processor architecture, TEE, SoC security, and deep learning accelerator design

2023.09 — 2025.09

M.S. in Computer Science & Information CommunicationMaster

Waseda University, Tokyo, Japan

School of Fundamental Science and Engineering · GPA: 3.53 / 4.00
MEXT Scholarship · Waseda University Tuition Waiver Scholarship

2019.09 — 2023.06

B.S. in Computer ScienceBachelor

Macau University of Science and Technology, Macau

Faculty of Computer Science and Engineering
Outstanding Graduate 2023 · 1st Place in University Debate Competition 2021

Research

Interests

⚙️

Processor Architecture

Heterogeneous accelerator design, memory hierarchy optimization, and RISC-V based system exploration.

🔒

Architecture Security

Trusted Execution Environments (TEE), SoC security, side-channel resilience, and secure-by-design hardware.

🧠

DL Accelerators

Deep learning accelerator architecture, hardware-software co-design, and efficient inference on edge devices.

Experience

Professional

2024.03 — Present

Computer Vision Algorithm Engineer

KGK International Technology Development Co., Ltd.

Tokyo, Japan

R&D on image recognition algorithms for next-generation AOI and AVI products. Developed pattern recognition and defect inspection pipelines using OpenCV.

2023.10 — Present

TEE & Processor Architecture

Waseda University

Tokyo, Japan

Working on processor and computer system architecture for Trusted Execution Environments (TEE). Research covers SoC security, deep learning accelerator development, and system integration.

2022.06 — 2022.07

Software Development Engineer Intern

Hunan Chuangbolong Intelligent Technology Co., Ltd.

Changsha, China

Developed Java-based applications as part of a project team. Analyzed user requirements, designed solutions, wrote requirements analysis reports, and coordinated backend development.

Projects

Projects

2023

TEE-Related Processor Architecture Research

Investigating processor and computer system architectures for Trusted Execution Environments. Covers SoC security, deep learning accelerator design, and system-level integration.

Waseda University · Ongoing

TEESoCSecurity
2021

Heterogeneous Processor Parallel Accelerator — Cache Design

Addressing performance overhead from CPU scaling and external storage access gaps. Built a Chipyard-based accelerator using RISC-V ISA, tag-based control mechanisms, and software-partitioned code transparency.

Macau University of Science and Technology

AcceleratorCacheRISC-V
2021

RISC-V rv32i Processor Built with Logisim-hust

Constructed a basic RISC-V rv32i instruction set processor using Logisim. Used rars assembler to compile and convert code to machine instructions for transparent architecture understanding.

Macau University of Science and Technology

RISC-VLogisimrv32i
2022

AI Shape-Matching Typing Software

Implemented DFS, BFS, A*, Greedy, and UCS search algorithms with a GUI to visualize real-time handwriting and computation cost comparisons.

Macau University of Science and Technology

AISearchGUI
2022

Star Wars Character Recognition via Computer Vision

Built a mobile camera-based recognition system using computer vision and machine learning to identify characters from real-time video feeds.

Macau University of Science and Technology

CVMLMobile

Skills

Technical & Languages

Programming

CC++Java ScalaPythonChisel VerilogJavaScriptHTML/CSS GitLinuxDocker

Frameworks & Tools

OpenCVSQLiteShell ChipyardRISC-V Logisim

Languages

Mandarin — Native English — TOEFL 104 Japanese — N2

Open Source

GitHub

DereLiu

github.com/DereLiu

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Contribution Activity

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