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論文 (234件)

    2023
  1. 川角 冬馬, 見神 広紀, 吉川 智哉, 細見 武郎, 追立 真吾, 木村 啓二, 笠原 博徳, "OSCAR自動並列化コンパイラによる並列化オーバヘッド削減のためのタスク融合手法を用いた実ラダーアプリケーションの並列化", 情報処理学会論文誌, Vol.65, No.2, pp.539-551, Feb. 2024.
  2. Fumiaki Onishi, Ryosei Otaka, Kazuki Fujita, Tomoki Suetsugu, Tohma Kawasumi, Toshiaki Kitamura, Hironori Kasahara, and Keiji Kimura, "Automatic Deep Learning Parallelization for Vector Multicore Chips with the OSCAR Parallelizing and the TVM Open-Source Deep Learning Compiler", Proc. of The 36th International Workshop on Languages and Compilers for Parallel Computing (LCPC 2023), Lexington, Kentucky, USA., Oct. 2023.
    3. 2022
  3. Tohma Kawasumi, Tsumura Yuta, Hiroki Mikami, Tomoya Yoshikawa, Takero Hosomi, Shingo Oidate, Keiji Kimura, Hironori Kasahara, "Parallelizing Factory Automation Ladder Programs by OSCAR Automatic Parallelizing Compiler", Proc. of the 35th International Workshop on Languages and Compilers for Parallel Computing (LCPC2022), Oct. 2022.
    4. 2021
  4. 木村 啓二, 梅田 弾, 笠原 博徳, "組込みシステムにおける並列化技術動向", システム／制御／情報, Vol.66, No.1, pp.2-7, Jan. 2022.
  5. Jixin Han, Tomofumi Yuki, Michelle Mills Strout, Dan Umeda, Hironori Kasahara, Keiji Kimura, "Parallelizing Compiler Translation Validation Using Happens-Before and Task-Set", 2021 Ninth International Symposium on Computing and Networking Workshops (CANDARW), pp.87-93, Nov. 2021.
  6. Hironori Kasahara, Keiji Kimura, Toshiaki Kitamura, Hiroki Mikami, Kazutaka Morita, Kazuki Fujita, Kazuki Yamamoto, Tohma Kawasumi, "OSCAR Parallelizing and Power Reducing Compiler and API for Heterogeneous Multicores : (Invited Paper)", 2021 IEEE/ACM SC'21 Workshop on Programming Environments for Heterogeneous Computing (PEHC), pp.10-19, Nov. 2021.
  7. Birk Martin Magnussen, Tohma Kawasumi, Hiroki Mikami, Keiji Kimura, and Hironori Kasahara, "Performance Evaluation of OSCAR Multi-target Automatic Parallelizing Compiler on Intel, AMD, Arm and RISC-V Multicores", The 34th International Workshop on Languages and Compilers for Parallel Computing(LCPC2021), Oct. 2021.
  8. Shaoshan Liu, Jean-Luc Gaudiot, Hironori Kasahara, "Engineering Education in the Age of Autonomous Machines", IEEE Computer, Vol.54(4), pp.66-69 , Apr. 2021.
    9. 2020
  9. Jean-Luc Gaudiot, Hironori Kasahara, "Computer Education in the Age of COVID-19", Computer, January 2020, IEEE Computer Society, Vol. 53, No. 10, pp.114-118, Oct. 2020.
    10. 2019
  10. Boma A. Adhi, Tomoya Kashimata, Ken Takahashi, Keiji Kimura, Hironori Kasahara, "Compiler Software Coherent Control for Embedded High Performance Multicore", IEICE Transaction on Electronics Special Section on “Low-Power and High-Speed Chips”, Vol. E103-C, No. 3, pp.85-97, Mar. 2020.
  11. Yoshitake Oki, Yuto Abe, Kazuki Yamamoto, Kohei Yamamoto, Tomoya Shirakawa, Akimasa Yoshida, Keiji Kimura, Hironori Kasahara, "Local Memory Mapping of Multicore Processors on an Automatic Parallelizing Compiler", IEICE Transaction on Electronics　Special Section on “Low-Power and High-Speed Chips”, Vol. E103-C, No. 3, pp.98-109, Mar. 2020.
  12. Tomoya Kashimata, Toshiaki Kitamura, Keiji Kimura, Hironori Kasahara, "Cascaded DMA Controller for Speedup of Indirect Memory Access in Irregular Applications", IA^3 2019: 9th Workshop on Irregular Applications: Architectures and Algorithms, Nov. 2019.
  13. Tohma Kawasumi, Ryota Tamura, Yuya Asada, Jixin Han, Hiroki Mikami, Keiji Kimura, Hironori Kasahara, "Fast and Highly Optimizing Separate Compilation for Automatic Parallelization", The 2019 International Conference on High Performance Computing & Simulation (HPCS 2019), Jul. 2019.
  14. Boma A. Adhi, Masayoshi Mase, Yuhei Hosokawa, Yohei Kishimoto, Taisuke Onishi, Hiroki Mikami, Keiji Kimura, Hironori Kasahara, "Software Cache Coherent Control by Parallelizing Compiler", Lecture Notes in Computer Science, Vol. LNCS 11403. Springer, 2019, pp.17-25, 2019.
    15. 2017
  15. Boma A. Adhi, Masayoshi Mase, Yuhei Hosokawa, Yohei Kishimoto, Taisuke Onishi, Hiroki Mikami, Keiji Kimura, Hironori Kasahara, "Software Cache Coherent Control by Parallelizing Compiler", 30th International Workshop on Languages and Compilers for Parallel Computing(LCPC), Oct. 2017.
  16. Hironori Kasahara, Keiji Kimura, Boma A. Adhi, Yuhei Hosokawa, Yohei Kishimoto,　Masayoshi Mase, "Multicore Cache Coherence Control by a Parallelizing Compiler", IEEE COMPSAC 2017 (The 41th IEEE Computer Society International Conference on Computers, Software & Applications), Jul. 2017.
    17. 2016
  17. Koichiro Yamashita, Chen Ao, Takahisa Suzuki, Yi Xu, Hongchun Li, Jun Tian, Keiji Kimura, Hironori Kasahara, "Architecture design for the environmental monitoring system over the winterseason", MobiWac '16: Proc of the 14th ACM International Symposium on Mobility Management and Wireless Access, pp.27-34, Nov. 2016.
  18. Jixin Han、Rina Fujino, Ryota Tamura, Mamoru Shimaoka, Hiroki Mikami, Moriyuki Takamura, Sachio Kamiya, Kazuhiko Suzuki, Takahiro Miyajima, Keiji Kimura, Hironori Kasahara, "Reducing Parallelizing CompilationTime by Removing Redundant Analysis", Systems, Programming, Languages and Applications: Software for Humanity (SPLASH), Oct. 2016.
  19. Kouhei Yamamoto, Tomoya Shirakawa, Yoshitake Oki, Akimasa Yoshida, Keiji Kimura, Hironori Kasahara, "Automatic Local Memory Management for Multicores Having Global Address Space", 29th International Workshop on Languages and Compilers for Parallel Computing(LCPC), Sep. 2016.
  20. Keiji Kimura, Gakuho Taguchi, Hironori Kasahara, "Accelerating Multicore Architecture Simulation Using Application Profile", 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Sep. 2016.
  21. Bui Duc Binh, Tomohiro Hirano, Hiroki Mikami, Hideo Yamamoto, Keiji Kimura, Hironori Kasahara, "Android Video Processing System Combined with Automatically Parallelized and Power Optimized Code by OSCAR Compiler", Journal of Information Processing (online), Vol. 24, No. 3, pp.504-511, May. 2016.
    22. 2015
  22. 梅田 弾, 鈴木 貴広, 見神 広紀, 木村 啓二, 笠原 博徳, "組み込み向けモデルベース開発アプリケーションのプロファイル情報を用いたマルチコア用マルチグレイン並列処理", 情報処理学会論文誌, Vol. 57, No. 2, pp.1-12, Feb. 2016
  23. Daichi Fukui, Mamoru Shimaoka, Hiroki Mikami, Dominic Hillenbrand, Hideo Yamamoto, Keiji Kimura, Hironori Kasahara, "Annotatable Systrace: An Extended Linux ftrace for Tracing a Parallelized Program", Systems, Programming, Languages and Applications: Software for Humanity (SPLASH), Oct.2015.
  24. Mamoru Shimaoka, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, "Coarse Grain Task Parallelization of Earthquake Simulator GMS Using OSCAR Compiler on Various cc-NUMA Servers", 28th International Workshop on Languages and Compilers for Parallel Computing(LCPC),Sep.2015.
  25. Dan Umeda, Takahiro Suzuki, Hiroki Mikami, Keiji Kimura, Hironori Kasahara, "Multigrain Parallelization for Model-based Design Applications Using the OSCAR Compiler", Proc. Of The 28nd International Workshop on Languages and Compilers for Parallel Computing (LCPC), Sep.2015.
    26. 2014
  26. Hasan Alkhatib, Paolo Faraboschi, Eitan Frachtenberg, Hironori Kasahara, Danny Lange, Phil Laplante, Arif Merchant, Dejan Milojicic, Karsten Schwan, "What Will 2022 Look Like? The IEEE CS 2022 Report", IEEE Computer Society Computer, Mar. 2015.
  27. Makoto Nakayama, Kenichi Yamazaki, Satoshi Tanaka, Hironori Kasahara,“Parallelization of Tree-to-TLV Serialization”, Proc. of 33rd IEEE International Performance Computing andCommunications Conference (IPCCC2014), Dec.2014.
  28. 梅田弾, 金羽木洋平, 見神広紀, 林明宏, 谷充弘（（株）デンソー）, 森裕司（（株）デンソー）, 木村啓二, 笠原博徳, "MATLAB/Simulinkで設計されたエンジン制御Cコードのマルチコア用自動並列化", 情報処理学会論文誌コンピューティングシステム, Vol. 55, No. 8, pp.1817-1829, Aug.2014.
  29. Tomohiro Hirano, Hideo Yamamoto, Shuhei Iizuka, Kohei Muto, Takashi Goto, Tamami Wake, Hiroki Mikami, Moriyuki Takamura, Keiji Kimura, Hironori Kasahara, "Evaluation of Automatic Power Reduction with OSCAR Compiler on Intel Haswell and ARM Cortex-A9 Multicores", The 27th International Workshop on Languages and Compilers for Parallel Computing(LCPC), Sep. 2014.
  30. 木村啓二, 笠原博徳, "グリーンコンピューティングの展望", 技術雑誌スマートグリッド2014.10 「特集スマートグリッドをささえる新技術」, Vol. 55, No. 14, pp.3-8, Oct. 2014.
  31. 中山誠, 山崎憲一（芝浦工大）, 田中聡（NTTドコモ）, 笠原博徳, "スレッド間パイプによる逐次化を用いたハッシュ表の並列構築手法", 電子情報通信学会論文誌. D, 情報・システム Vol. J97-D(10), pp1541-1552, Oct. 2014.
    32. 2013
  32. 木村啓二, 笠原博徳, "低消費電力コンピューティングを実現するマルチコア技術", 電子情報通信学会誌2月号　pp.133-139, Feb. 2014.
  33. Makoto Nakayama, Kenichi Yamazaki(Shibaura Institute of Technology), Satoshi Tanaka(NTT DOCOMO), Hironori Kasahara, "Dynamic Profiling and Feedback Framework for Reduce-side Join", The 2013 International Symposium on MapReduce and Big Data Infrastructure (MR.BDI 2013), Sydney, Australia, Dec. 2013.
  34. 中山誠, 山崎憲一（芝浦工大）, 田中聡（NTTドコモ）, 笠原博徳, "重複部分木情報を利用した事前圧縮を特徴とするSerDeの開発と評価", 電子情報通信学会論文誌. D, 情報・システム Vol. J96-D(10), pp2089-2100, Oct. 2013.
  35. Hideo Yamamoto, Tomohiro Hirano, Kohei Muto, Hiroki Mikami, Takashi Goto, Dominic Hillenbrand, Moriyuki Takamura, Keiji Kimura, and Hironori Kawahara, "OSCAR Compiler Controlled Multicore Power Reduction on Android Platform", The 26th International Workshop on Languages and Compilers for Parallel Computing,(LCPC2013), Qualcomm Research Silicon Valley, US, Sep. 2013.
  36. Dominic Hillenbrand, Yuuki Furuyama, Akihiro Hayashi, Hiroki Mikami, Keiji Kimura and Hironori Kasahara, "Reconciling Application Power Control and Operating Systems for Optimal Power and Performance", 8th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC (ReCoSoC2013), Darmstadt, Germany, Jul. 2013.
  37. Dan Umeda, Yohei Kanehagi, Hiroki Mikami, Akihiro Hayashi, Keiji Kimura, Hironori Kasahara, "Automatic Parallelization of Hand Written Automotive Engine Control Codes Using OSCAR Compiler", 17th Workshop on Compilers for Parallel Computing (CPC2013), Lyon, France, Jul. 2013.
  38. Keiji Kimura, Cecilia Gonzales-Alvarez, Akihiro Hayashi, Hiroki Mikami, Mamoru Shimaoka, Jun Shirako, Hironori Kasahara, "OSCAR API v2.1: Extensions for an Advanced Accelerator Control Scheme to a Low-Power Multicore API", 17th Workshop on Compilers for Parallel Computing (CPC2013), Lyon, France, Jul. 2013.
  39. Dominic Hillenbrand, Akihiro Hayashi, Hideo Yamamoto, Keiji Kimura, Hironori Kasahara, "Automatic Parallelization, Performance Predictability and Power Control for Mobile-Applications", COOL Chips XVI, IEEE Symposium on Low Power and High-Speed, Apr. 2013.
  40. Yohei Kanehagi, Dan Umeda, Akihiro Hayashi, Keiji Kimura, Hironori Kasahara, "Parallelization of Automotive Engine Control Software On Embedded Multi-core Processor Using OSCAR Compiler", COOL Chips XVI, IEEE Symposium on Low Power and High-Speed, Apr. 2013.
    41. 2012
  41. Cecilia Gonzalez-Alvarez, Haruku Ishikawa, Akihiro Hayashi, Daniel Jimenez-Gonzalez, Carlos Alvarez, Keiji Kimura, Hironori Kasahara, "Automatic Design Exploration Framework for Multicores with Reconfigurable Accelerators", 7th Workshop on Reconfigurable Computing (WRC) 2013, held in conjuction with HiPEAC conference 2013, Berlin, Jan. 2013.
  42. Yasir I Al-Dosary, Keiji Kimura, Hironori Kasahara, and Seinosuke Narita, "Enhancing the Performance of a Multiplayer Game by Using a Parallelizing Compiler", 17th International Conference on Computer Games: AI, Animation, Mobile, Educational & Serious Games, Jul. 2012.
  43. 笠原博徳, "グリーンコンピューティングのための低消費電力マルチコア技術", 特技 懇誌 特許庁, Vol. 265, pp.31-42, May. 2012.
    44. 2011
  44. Akihiro Hayashi, Mamoru Shimaoka, Hiroki Mikami, Masayoshi Mase, Yasutaka Wada, Jun Shirako, Keiji Kimura, and Hironori Kasahara, "OSCAR Parallelizing Compiler and API for Real-time Low Power Heterogeneous Multicores", 16th Workshop on Compilers for Parallel Computing(CPC2012), Padova, Italy, Jan. 2012. (To appear)
  45. 林明宏, 和田康孝, 渡辺岳志, 関口威, 間瀬正啓, 白子準, 木村啓二, 笠原博徳, "ヘテロジニアスマルチコア向けソフトウェア開発フレームワーク及びAPI", 情報処理学会論文誌コンピューティングシステム(ACS36), Vol.5, No.1, pp.68-79, Nov. 2011.
  46. Yasutaka Wada, Akihiro Hayashi, Takeshi Masuura, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, and Hironori Kasahara, "A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture", Transactions on High-Performance Embedded Architectures and Compilers IV,Lecture Note in Computer Science, Springer, Vol. 6760, pp.215-233, Nov. 2011.
  47. Hiroki Mikami, Shumpei Kitaki, Masayoshi Mase, Akihiro Hayashi, Mamoru Shimaoka, Keiji Kimura, Masato Edahiro, and Hironori Kasahara, "Evaluation of Power Consumption at Execution of Multiple Automatically Parallelized and Power Controlled Media Applications on the RP2 Low-power Multicore", Proc. of LCPC 2011(The 24th International Workshop on Languages and Compilers for Parallel Computing ), Colorado State University, Fort Collins, Colorado, Sept 8-10, 2011.
  48. Osamu NISHII, Yoichi YUYAMA, Masayuki ITO, Yoshikazu KIYOSHIGE,YusukeNITTA, Makoto ISHIKAWA, Tetsuya YAMADA, Junichi MIYAKOSHI,YasutakaWADA, Keiji KIMURA, Hironori KASAHARA, and Hideo MAEJIMA,"A 45-nm37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 BitInstruction-SetGeneral-Purpose Core",IEICE TRANSACTIONS on Electronics, Vol. E94-C, No. 4,pp.663-669, Apr. 2011.
    49. 2010
  49. Akihiro Hayashi, Yasutaka Wada, Takeshi Watanabe, Takeshi Sekiguchi,Masayoshi Mase, Jun Shirako, Keiji Kimura, and Hironori Kasahara, "Parallelizing Compiler Framework and API for Power Reduction and Software Productivity of Real-time Heterogeneous Multicores", Lecture Notes in Computer Science, Springer, Vol.6548, pp.184-198, Feb. 2011.
  50. Akihiro Hayashi, Yasutaka Wada, Takeshi Watanabe, Takeshi Sekiguchi, Masayoshi Mase, Jun Shirako, Keiji Kimura and Hironori Kasahara, "Parallelizing Compiler Framework and API for Power Reduction and Software Productivity of Real-time Heterogeneous Multicores", Proc. of The 23rd International Workshop on Languages and Compilers for Parallel Computing (LCPC2010), Oct. 2010.
  51. Masayoshi Mase, Yuto Onozaki, Keiji Kimura and Hironori Kasahara, "Parallelizable C and Its Performance on Low Power High Performance Multicore Processors", Proc. of 15th Workshop on Compilers for Parallel Computing 2010, Jul. 2010.
  52. Takumi Nito, Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Osamu Nishii, Atsushi Hasegawa, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Koichi Terada, Tohru Nojiri, Masashi Takada, Makoto Satoh, Hiroyuki Mizuno, Kunio Uchiyama, Yasutaka Wada, Akihiro Hayashi, Keiji Kimura, Hironori Kasahara, and Hideo Maejima, "A 45nm Heterogeneous Multi-core SoC Supporting an over 32-bits Physical Address Space for Digital Appliance", Proc. of IEEE Symposium on Low-Power and High Speed Chips (COOL Chips XIII), pp.225-238, Apr. 2010.
  53. Keiji Kimura, Masayoshi Mase, Hiroki Mikami, Takamichi Miyamoto, Jun Shirako and Hironori Kasahara, "OSCAR API for Real-time Low-Power Multicores and Its Performance on Multicores and SMP Servers", Lecture Notes in Computer Science, Springer, Vol.5898, pp.188-202, Oct. 2010.
    54. 2009
  54. Masafumi Onouchi, Keisuke Toyama, Toru Nojiri, Makoto Sato, Masayoshi Mase, Jun Shirako, Mikiko Sato, Masashi Takada, Masayuki Ito, Hiroyuki Mizuno, Mitaro Namiki, Keiji Kimura, Hironori Kasahara, "瞬時電源遮断技術を用いたマルチコアＳｏＣ向け省電力ソフトウェア実行環境の提案", 社団法人電子情報通信学会 信学技報, Jan. 2010.
  55. Masafumi Onouchi, Keisuke Toyama, Toru Nojiri, Makoto Sato, Masayoshi Mase, Jun Shirako, Mikiko Sato, Masashi Takada, Masayuki Ito, Hiroyuki Mizuno, Mitaro Namiki, Keiji Kimura, Hironori Kasahara, "Green Multicore-SoC Software-Execution Framework with Timely-Power-Gating Scheme", Proc. of 2009 International Conference on Parallel Processing, pp.510-517, Sep. 2009.
  56. Y. Yuyama, M. Ito, Y. Kiyoshige, Y. Nitta, S. Matsui, O. Nishii, A. Hasegawa, M. Ishikawa, T. Yamada, J. Miyakoshi, K. Terada, T. Nojiri, M. Satoh, H. Mizuno, K. Uchiyama, Y. Wada, K. Kimura, H. Kasahara, H. Maejima, "A 45nm 37.3GOPS/W Heterogeneous Multi-Core SoC", 2010 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC 2010), San Francisco, Feb. 8, 2010.
  57. Keiji Kimura, Masayoshi Mase, Hiroki Mikami, Takamichi Miyamoto, Jun Shirako and Hironori Kasahara, "OSCAR API for Real-time Low-Power Multicores and Its Performance on Multicores and SMP Servers", Proc. of The 22nd International Workshop on Languages and Compilers for Parallel Computing (LCPC2009), Oct. 2009.
  58. 間瀬正啓,中川亮,大國直人, 白子準, 木村啓二, 笠原博徳, "マルチコア上でのOSCAR APIを用いた並列化コンパイラによる低消費電力化手法", 情報処理学会論文誌コンピューティングシステム, Vol. 2, No. 3, pp.96-106, Sep. 2009.
  59. 中野啓史, 桃園拓, 間瀬正啓, 木村啓二, 笠原博徳, "マルチコアプロセッサ上での粗粒度タスク並列処理のためのコンパイラによるローカルメモリ管理手法", 情報処理学会論文誌コンピューティングシステム, Vol. 2, No. 2, pp.63-74, Jul. 2009.
  60. 間瀬正啓, 村田雄太, 木村啓二, 笠原博徳, "自動並列化のためのElement-Sensitiveポインタ解析", 情報処理学会論文誌プログラミング(PRO), Vol. 2, No. 5, pp.1-12, May. 2009.
    61. 2008
  61. Fumiyo Takano, Yoshitaka Maekawa, Hironori Kasahara, "Multiple-paths Search with Concurrent Thread Scheduling for Fast AND/OR Tree Search", Proc. of International Conference on Complex, Intelligent and Software Intensive Systems (CISIS 2009), Mar. 2009.
  62. Fumiyo Takano, Yoshitaka Maekawa, Hironori Kasahara, "Parallel and Concurrent Search for Fast AND/OR Tree Search on Multicore Processors", Proc. of the IASTED International Conference on Parallel and Distributed Computing and Networks (PDCN 2009), Feb. 2009.
  63. Hiroki Mikami, Jun Shirako, Masayoshi Mase, Takamichi Miyamoto, Hirofumi Nakano, Fumiyo Takano, Akihiro Hayashi, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, "Performance of OSCAR Multigrain Parallelizing Compiler on Multicore Processors", Proc. of 14th Workshop on Compilers for Parallel Computing(CPC 2009), Jan. 2009.
  64. Takamichi Miyamoto, Saori Asaka, Hiroki Mikami, Masayoshi Mase, Yasutaka Wada, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara, "Parallelization with Automatic Parallelizing Compiler Generating Consumer Electronics Multicore API", Proc. of IEEE International Symposium on Advances in Parallel and Distributed Computing Techniques (APDCT-08), Dec. 2008.
  65. 宮本孝道, 浅香沙織, 見神広紀, 間瀬正啓, 木村啓二, 笠原博徳, "情報家電用マルチコア並列化APIを生成する自動並列化コンパイラによる並列化の評価", 情報処理学会論文誌　コンピューティングシステム, Vol. 1, No. 3, pp.83-95, Dec. 2008.
  66. Jun Shirako, Keiji Kimura, Hironori Kasahara, "Power Reduction Controll for Multicores in OSCAR Multigrain Parallelizing Compiler", Proc. of International SoC Design Conference　(ISOCC 2008), Nov. 2008.
  67. Jun Shirako, Hironori Kasahara, Vivek Sarkar, "Language Extensions in Support of Compiler Parallelization", Lecture Notes in Computer Science, Springer, Vol. 5234, pp.78-94, Oct. 2008.
  68. 和田 康孝, 林 明宏, 益浦 健, 白子 準, 中野 啓史, 鹿野 裕明, 木村啓二, 笠原博徳, "ヘテロジニアスマルチコア上でのスタティックスケジューリングを用いたMP3エンコーダの並列化", 情報処理学会論文誌コンピューティングシステム, Vol. 1, No. 1, pp.105-119, Jun. 2008.
  69. Yasutaka Wada, Akihiro Hayashi, Takeshi Masuura, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara, "Parallelizing Compiler Cooperative Heterogeneous Multicore", Proc. of Workshop on Software and Hardware Challenges of Manycore Platforms (SHCMP 2008), Jun. 2008.
  70. Yutaka Yoshida, Masayuki Ito, Kiyoshi Hayase, Tomoichi Hayashi, Osamu Nishii, Toshihiro Hattori, Jun Sakiyama, Masashi Takada, Kunio Uchiyama, Jun Shirako, Masayoshi Mase, Keiji Kimura, Hironori Kasahara, "An 8 CPU SoC with Independent Power-off Control of CPUs and Multicore Software Debug Function", Proc. of IEEE Cool Chips XI: Symposium on Low-Power and High-Speed Chips 2008, Apr. 2008.
  71. Hiroaki Shikano, Masaki Ito, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Masafumi Onouchi, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, "Heterogeneous Multi-core Architecture that Enables 54x AAC-LC Stereo Encoding", IEEE Journal of Solid-State Circuits, Vol. 43, No. 4, pp.902-910, Apr. 2008.
  72. Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, "Power-Aware Compiler Controllable Chip Multiprocessor", IEICE TRANS. ELECTRON, Vol. E91-C, No. 4, pp.432-439, Apr. 2008.
    73. 2007
  73. 笠原博徳, "情報家電用マルチコア・プロセッサ", 電気学会誌, Vol. 128, No. 3, pp.172-175, Mar. 2008.
  74. Masayuki Ito, Toshihiro Hattori, Yutaka Yoshida, Kiyoshi Hayase, Tomoichi Hayashi, Osamu Nishii, Yoshihiko Yasu, Atsushi Hasegawa, Masashi Takada, Masaki Ito, Hiroyuki Mizuno, Kunio Uchiyama, Toshihiko Odaka, Jun Shirako, Masayoshi Mase, Keiji Kimura, Hironori Kasahara, "An 8640 MIPS SoC with Independent Power-off Control of 8 CPU and 8 RAMS by an Automatic Parallelizing Compiler", Proc. of IEEE International Solid State Circuits Conference (ISSCC2008), Feb. 2008.
  75. Hiroaki Shikano, Masaki Ito, Kunio Uchiyama, Toshihiko Odaka, Akihiro Hayashi, Takeshi Masuura, Masayoshi Mase, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, "Software-Cooperative Power-Efficient Heterogeneous Multi-Core for Media Processing", Proc. of 13th Asia and South Pacific Design Automation Conference (ASP-DAC 2008), Jan. 2008.
  76. Jun Shirako, Munehiro Yoshida, Naoto Oshiyama, Yasutaka Wada, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara, "Performance Evaluation of Compiler Controlled Power Saving Scheme", Lecture Notes in Computer Science, Springer, Vol. 4759, pp.480-493, Jan. 2008.
  77. Jun Shirako, Hironori Kasahara, Vivek Sarkar, "Language Extensions in Support of Compiler Parallelization", Proc. of The 20th International Workshop on Languages and Compilers for Parallel Computing (LCPC2007), University of Illinois at Urbana-Champaign, Siebel Center for Computer Science, Urbana, Illinois, Oct. 2007.
  78. M. Mase, D. Baba, H. Nagayama, H. Tano, T. Masuura, T. Miyamoto, J. Shirako, H. Nakano, K. Kimura, H. Kasahara, "Multigrain Parallelization of Restricted C Programs on SMP Servers and Low Power Multicores", The 20th International Workshop on Languages and Compilers for Parallel Computing (LCPC2007), Oct. 2007.
  79. Masaki Ito, Takashi Todaka, Takanobu Tsunoda, Hiroshi Tanaka, Tomoyuki Kodama, Hiroaki Shikano, Masafumi Onouchi, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, "Heterogeneous Multiprocessor on a Chip Which Enables 54x AAC-LC Stereo Encoding", Proc. of 2007 Symposia on VLSI TEchnology and Circuits, Jun. 2007.
  80. 鹿野裕明, 鈴木裕貴, 和田康孝, 白子準, 木村啓二, 笠原博徳, "MP3エンコーダを用いたOSCARヘテロジニアスチップマルチプロセッサの性能評価", 情報処理学会論文誌コンピューティングシステム, Vol. 48, No. SIG8（ACS18), pp.141-152, May. 2007.
  81. Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara, "Compiler Control Power Saving Scheme for Multi Core Processors", Lecture Notes in Computer Science, Springer, Vol. 4339, pp.362-376, May. 2007.
    82. 2006
  82. Y. Yoshida, T. Kamei, K. Hayase, S. Shibahara, O. Nishii, T. Hattori, A. Hasegawa, M. Takada, N. Irie, K. Uchiyama, T. Odaka, K. Takada, K. Kimura, H. Kasahara, "A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption", Proc. of 2007 IEEE International Solid-State Circuits Conference(ISSCC2007), Feb. 2007.
  83. 白子 準, 吉田 宗弘, 押山 直人, 和田 康孝, 中野 啓史, 鹿野 裕明, 木村 啓二, 笠原 博徳, "マルチコアプロセッサにおけるコンパイラ制御低消費電力化手法", 情報処理学会論文誌コンピューティングシステム, Vol. 47, No. SIG12(ACS15), pp.147-158, Sep. 2006.
  84. Jun Shirako, Munehiro Yoshida, Naoto Oshiyama, Yasutaka Wada, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara, "Performance Evaluation of Compiler Controlled Power Saving Scheme", Proc. of 20th ACM International Conference on Supercomputing Workshop on Advanced Low Power Systems(ALPS2006), Jul. 2006.
  85. Hiroaki Shikano, Yuki Suzuki, Yasutaka Wada, Jun Shirako, Keiji Kimura, Hironori Kasahara, "Performance Evaluation of Heterogeneous Chip Multi-Processor with MP3 Audio Encoder", Proc. of IEEE Symposium on Low-Power and High Speed Chips (COOL Chips IX), pp.349-363, Apr. 2006.
    86. 2005
  86. Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara, "Parallelizing Compilation Scheme for Reduction of Power Consumption of Chip Multiprocessors", Proc. of 12th Workshop on Compilers for Parallel Computers　(CPC 2006), pp.426-440, Jan. 2006.
  87. 笠原博徳, 木村啓二, "1.マルチコア化するマイクロプロセッサ", 情報処理 「特集　マルチコアにおけるソフトウェア」, Vol. 47, No. 1, pp.10-16, Jan. 2006.
  88. 木村啓二, 笠原博徳, "2.マルチコアにおけるプログラミング", 情報処理 「特集　マルチコアにおけるソフトウェア」, Vol. 47, No. 1, pp.17-23, Jan. 2006.
  89. Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara, "Compiler Control Power Saving Scheme for Multi Core Processors", Proc. of The 18th International Workshop on Languages and Compilers for Parallel Computing (LCPC2005), Oct. 2005.
  90. 小高 剛, 中野 啓史, 木村 啓二, 笠原　博徳, "チップマルチプロセッサ上でのMPEG2エンコードの並列処理", 情報処理学会論文誌, Vol. 46, No. 9, pp.2311-2325, Sep. 2005.
  91. Kazuhisa Ishizaka, Takamichi Miyamoto, Jun Shirako, Motoki Obata, Keiji Kimura, Hironori Kasahara, "Performance of OSCAR Multigrain Parallelizing Compiler on SMP Servers", Lecture Notes in Computer Science, Springer, Vol. 3602, pp.319, 2005.
  92. Motoki Obata, Jun Shirako, Hiroki Kaminaga, Kazuhisa Ishizaka, Hironori Kasahara, "Hierarchical Parallelism Control for Multigrain Parallel Processing", Lecture Notes in Computer Science, Springer, Vol. 2481, pp.31-44, 2005.
    93. 2004
  93. 石坂 一久, 小幡 元樹, 笠原 博徳, "配列間パディングを用いた粗粒度タスク間キャッシュ最適化", 情報処理学会論文誌, Vol. 45, No. 4, Apr. 2004.
  94. 白子 準,長澤 耕平,石坂 一久,小幡 元樹,笠原 博徳, "マルチグレイン並列性向上のための選択的インライン展開手法", 情報処理学会論文誌, Vol. 45, No. 5, pp.1354-1356, May. 2004.
  95. Keiji Kimura, Yasutaka Wada, Hirofumi Nakano, Takeshi Kodaka, Jun Shirako, Kazuhisa Ishizaka, Hironori Kasahara, "Multigrain Parallel Processing on Compiler Cooperative Chip Multiprocessor", Proc. of 9th Workshop on Interaction between Compilers and Computer Architectures (INTERACT-9), Feb. 2005.
  96. Kazuhisa Ishizaka, Takamichi Miyamoto, Jun Shirako, Motoki Obata, Keiji Kimura, and Hironori Kasahara, "Performance of OSCAR Multigrain Parallelizing Compiler on SMP Servers", Proc. of 17th International Workshop on Languages and Compilers for Parallel Computing(LCPC2004), Sep. 2004.
    97. 2003
  97. Keiji Kimura, Takeshi Kodaka, Motoki Obata, Hironori Kasahara, "Multigrain Parallel Processing on Compiler Cooperative OSCAR Chip Multiprocessor Architecture", The IEICE Transactions on Electronics, Special Issue on High-Performance and Low-Power System LSIs and Related Technologies, Vol. 86-C, No. 4, pp.570-579, Apr. 2003.
  98. 小幡 元樹, 白子 準, 神長 浩気, 石坂 一久, 笠原 博徳, "マルチグレイン並列処理のための階層的並列性制御手法", 情報処理学会論文誌, Vol. 44, No. 4, Apr. 2003.
  99. 笠原博徳, "最先端の自動並列化コンパイラ技術", 情報処理, Vol. 44, No. 4, pp.384-392, Apr. 2003.
  100. Hirofumi Nakano, Kazuhisa Ishizaka, Motoki Obata, Keiji Kimura, Hironori Kasahara, "Static Coarse Grain Task Scheduling with Cache Optimization Using OpenMP", International Journal of Parallel Programming, Vol. 31, No. Issue 3, pp.211-223, Jun. 2003.
  101. K. Ishizaka, M. Obata and H. Kasahara, "Cache Optimization for Coarse Grain Task Parallel Processing using Inter-Array Padding", Proc. of 16th International Workshop on Languages and Compilers for Parallel Computing(LCPC2003), pp.64-76, Oct. 2003.
  102. Takeshi Kodaka, Hirohumi Nakano, Keiji Kimura and Hironori Kasahara, "Parallel Processing using Data Localization for MPEG2 Encoding on OSCAR Chip Multiprocessor", Proc. of International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'04), Jan. 2004.
  103. Hirofumi Nakano, Takeshi Kodaka, Keiji Kimura, Hironori Kasahara, "Memory Management for Data Localization on OSCAR Chip Multiprocessor", Proc. of International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'04), Jan. 2004.
  104. Jun shirako, Kouhei Nagasawa, Kazuhisa Ishizaka, Motoki Obata, Hironori Kasahara, "Selective Inline Expansion for Improvement of Multi Grain Parallelism", The IASTED International Conference on PARALLEL AND DISTRIBUTED COMPUTING AND NETWORKS(PDCN2004), Feb. 2004.
    105. 2002
  105. 飛田 高雄,笠原 博徳, "標準タスクグラフセットを用いた実行時間最小マルチプロセッサスケジューリングアルゴリズムの性能評価", 情報処理学会論文誌, Vol. 43, No. 4, Apr. 2002.
  106. 石坂 一久,中野 啓史,八木 哲志,小幡 元樹,笠原 博徳, "共有メモリマルチプロセッサ上でのキャッシュ最適化を考慮した粗粒度タスク並列処理", 情報処理学会論文誌, Vol. 43, No. 4, Apr. 2002.
  107. Hirofumi Nakano, Kazuhisa Ishizaka, Motoki Obata, Keiji Kimura, Hironori Kasahara, "Static Coarse Grain Task Scheduling with Cache Optimization Using OpenMP", Proc. of WOMPEI, pp.479-489, 2002.
  108. Motoki Obata, Jun Shirako, Hiroki Kaminaga, Kazuhisa Ishizaka, Hironori Kasahara, "Hierarchical Parallelism Control for Multigrain Parallel Processing", Proc. of 15th International Workshop on Languages and Compilers for Parallel Computing (LCPC2002), Aug. 2002.
  109. H.Kasahara, M.Obata, K.Ishizaka, K.Kimura, H.Kaminaga, H.Nakano, K.Nagasawa, A.Murai, H.Itagaki and J.Shirako, "Multigrain Automatic Parallelization in Japanese Millenium Project IT21 Advanced Parallelizing Compiler", Proc. of IEEE PARELEC (IEEE International Conference on Parallel Computingin Electrical Engineering),Warsaw,Poland, pp.105-111, Sep. 2002.
  110. 小高 剛, 内田 貴之, 木村 啓二, 笠原　博徳, "シングルチップマルチプロセッサにおけるJPEGエンコーディングのマルチグレイン並列処理", 情報処理学会ハイパフォーマンスコンピューティング システム論文誌, Vol. 43, No. Sig.6(HPS5), pp.153-162, Sep. 2002.
  111. Takao Tobita, Hironori Kasahara, "A standard task graph set for fair evaluation of multiprocessor scheduling algorithms", Journal of scheduing, John Wiley & Sons Ltd, Vol. 5, No. 5, pp.379-394, Oct. 2002.
  112. Hironori Kasahara, Motoki Obata, Kazuhisa Ishizaka, Keiji Kimura, Hiroki Kaminaga, Hirofumi Nakano, Kouhei Nagasawa,Akiko Murai,Hiroki Itagaki, Jun Shirako, "Performance of Multigrain Parallelization in Japanese Millennium Project IT21 Advanced Parallelizing Compiler", Proc. of 10th International Workshop on Compilers for Parallel Computers (CPC) Amsterdam, Netherland, Jan. 2003.
  113. Keiji Kimura, Takeshi Kodaka, Motoki Obata, Hironori Kasahara, "Multigrain Parallel Processing on OSCAR CMP", Proc. of International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems(IWIA'03), pp.56-65, Jan. 2003.
    114. 2001
  114. 木村 啓二, 加藤 孝幸, 笠原 博徳, "近細粒度並列処理用シングルチップマルチプロセッサにおけるプロセッサコアの評価", 情報処理学会論文誌, Vol. 42, No. 4, pp.692-703, Apr. 2001.
  115. 小出 洋, 笠原 博徳, "メタスケジューリング--自動並列分散処理の試み", bit, 共立出版, Vol. 33, No. 4, pp.10-14, Apr. 2001.
  116. 笠原 博徳, 小幡 元樹, 石坂 一久, "共有メモリマルチプロセッサシステム上での粗粒度タスク並列処理", 情報処理学会論文誌, Vol. 42, No. 4, Apr. 2001.
  117. Motoki Obata, Kazuhisa Ishizaka, Hironori Kasahara, "Automatic Coarse Grain Task Parallel ProcessingUsing OSCAR Multigrain Parallelizing Compiler", Ninth International Workshop on Compilers for ParallelComputers(CPC 2001), Edinburgh, Scotland UK, pp.173-182, Jun. 2001.
  118. Akimasa Yoshida, Satoshi Yagi, Hironori Kasahara, "A Data Localization Scheme for Coarse Grain Task Parallel Processing on Shared Memory Multiprocessors", Proc. of IEEE International Workshop on Advanced Compiler Technology for High Performance and Embedded Systems, pp.111-118, Jul. 2001.
  119. Kazuhisa Ishizaka, Motoki Obata, Hironori Kasahara, "Coarse Grain Task Parallel Processing with CacheOptimization on Shared Memory Multiprocessor", Proc. of 14th International Workshop on Languages and Compilers for Parallel Computing (LCPC2001), pp.352-365, Aug. 2001.
  120. Takeshi Kodaka, Keiji Kimura, Hironori Kasahara, "Multigrain Parallel Processing for JPEG Encodingon a Single Chip Multiprocessor", Proc. of International Workshop on Innovative Architecture for FutureGeneration High-Performance Processors and Systems (IWIA'02), pp.57-63, Jan. 2002.
  121. S.HASHIMOTO, S.NARITA, H. KASAHARA, K.SHIRAI, T.KOBAYASHI, A.TAKANISHI, S.SUGANO, J. YAMAGUCHI, H.SAWADA, H.TAKANOBU, K.SHIBUYA, T.MORITA, T.KURATA, N.ONOE, K.OUCHI, T.NOGUCHI, Y.NIWA, S.NAGAYAMA, H.TABAYASHI, I,MATSUI, M.OBATA, H.MATSUZAKI, A.MURASUGI, T.KOBAYASHI, S.HARUYAMA, T.OKADA, Y. HIDAKI, Y.TAGUCHI, K.HOASHI, E.MORIKAWA, Y.IWANO, D.ARAKI, J.SUZUKI, M.YOKOYAMA, I.DAWA, D.NISHINO, S.INOUE, T.HIRANO, E.SOGA, S.GEN, T.YANADA, K.KATO, S.SAKAMOTO, Y.ISHII, S.MATSUO, Y.YAMAMOTO, K.SATO, T.HAGIWARA, T.UEDA, N.HONDA, K.HASHIMOTO, T.HANAMOTO, S.KAYABA, T.KOJIMA, H.IWATA, H.KUBODERA, R.MATSUKI, T.NAKAJIMA, K.NITTO, D.YAMAMOTO, Y.KAMIZAKI, S.NAGAIKE, Y.KUNITAKE AND S.MORITA, "Humanoid Robots in Waseda University---Hadaly-2 and WABIAN", Autonomous Robots, 2002Kluwer Academic Publishers. Manufactured in The Netherlands., Vol. 12, No. 1, pp.25-38, Jan. 2002.
    122. 2000
  122. Takao Tobita, Masayoshi Kohda, Hironori Kasahara, "Performance Evaluation of Minimum Execution Time Multiprocessor Scheduling Algorithms Using Standard Task Graph Set", Proc. of the 2000 Int'l Conf. on Parallel and Distributed Processing Techniques and Applications (PDPTA'2000), pp.745-751, Jun. 2000.
  123. Hironori Kasahara, Motoki Obata, Kazuhisa Ishizaka, "Automatic Coarse Grain Task Parallel Processing on SMP using OpenMP", Proc. of 13th International Workshop on Languages and Compilers for Parallel Computing (LCPC'00), pp.189-207, Aug. 2000.
  124. Kazuhisa Ishizaka, Hironori Kasahara, Motoki Obata, "Coarse-grain Task Parallel Processing using the OpenMP backend of the OSCAR Multigrain Parallelizing Compiler", Proc. of Third International Symposium, ISHPC 2000, pp.352-365, Oct. 2000.
  125. Keiji Kimura, Hironori Kasahara, "Evaluation of Single Chip Multiprocessor Core Architecture with Near Fine Grain Parallel Processing ", Proc. of International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems(IWIA'01), Jan. 2001.
  126. 小出 洋, 山岸 信寛, 武宮 博, 笠原 博徳, "資源情報サーバにおける資源情報予測の評価", 情報処理学会論文誌, Vol. 42, No. SIG03, pp.65-73, Mar. 2001
    127. 1999
  127. 吉田 明正, 越塚 健一, 岡本 雅巳, 笠原 博徳, "階層型粗粒度並列処理における同一階層内ループ間データローカライゼーション手法", 情報処理学会論文誌, Vol. 40, No. 5, pp.2054-2063, May. 1999.
  128. 木村 啓二, 尾形 航, 岡本 雅巳, 笠原 博徳, "シングルチップマルチプロセッサ上での近細粒度並列処理", 情報処理学会論文誌, Vol. 40, No. 5, pp.1924-1934, May. 1999.
  129. 岡本 雅巳, 小幡 元樹, 松井 巌徹, 松崎 秀則, 笠原 博徳, 成田 誠之助, "マルチグレイン並列化FORTRANコンパイラ", 情報処理学会論文誌, Vol. 40, No. 12, pp.4296-4308, Dec. 1999.
  130. 飛田 高雄, 笠原 博徳, "A Standard Task Graph Set for Fair Evaluation of Multiprocessor Scheduling Algorithms", Proc. ICS99 Workshop, pp.71-77, Jun. 1999.
  131. H. Koide, T. Hirayama, A. Murasugi, T. Hayashi, H. Kasahara, "Meta-scheduling for a Cluster of　Supercomputers", Proc. ICS99 Workshop, pp.63-69, Jun. 1999.
  132. 笠原 博徳, 古郷 誠, 飛田 高雄, 増田 高史, 田中 崇久, "An Automatic Coarse Grain Parallel Processing Scheme Using Multiprocessor Scheduling Algorithms Considering Overlap of Task Execution and Data Transfer", Proc. SCI99 and ISAS99, Vol. 9, pp.82-89, Aug. 1999.
  133. 木村 啓二, 笠原 博徳, "Near Fine Grain Parallel Processing Using Static Scheduling on Single Chip Multiprocessors", Proc. International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'99), IEEE Computer Society Press, pp.23-31, Nov. 1999.
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  134. H. Kasahara and A. Yoshida, "A Data-Localization Compilation Scheme Using Partial Static Task Assignment for Fortran Coarse Grain Parallel　Processing", Journal of Parallel Computing, Special Issue on Languages and Compilers for parallel Computers, pp.579-596, May. 1998.
  135. 小幡 元樹, 前川 仁孝, 若尾 真治, 小貫 天, 笠原 博徳, "電磁界解析における有限要素・境界要素併用法の並列処理手法", 電気学会論文誌 A (基礎・材料・共通部門誌), Vol. 118-A, No. 4, pp.377-379, Apr. 1998.
  136. A. YOSHIDA, Y. UJIGAWA, M. OBATA, K. KIMURA, and H. KASAHARA, "Data-Localization among Doall and Sequential Loops in Coarse Grain Parallel Processing", Seventh Workshop on Compilers for Parallel Computers (Linkoping, Sweden), pp.266-277, 1998/6/29 - /7/1.
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    138. 1997
  138. A.Yoshida, K. Koshizuka, W. Ogata, H. Kasahara, "Data-Localization Scheduling inside Processor-Cluster for Multigrain Parallel Processing", 電子情報通信学会英文論文誌, Vol. E80-D, No. 4, pp.473-478, Apr. 1997.
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  144. W. Ogata, A. Yoshida, M. Okamoto, K. Kimura, H. Kasahara, "Near Fine Grain Parallel Processing without Explicit Synchronization on a Multiprocessor System", Proc. of Sixth Workshop on Compilers for Parallel Computers (Aachen, Germany), Dec. 1996.
  145. 前川 仁孝, 高井 峰生, 伊藤 泰樹, 西川 健, 笠原 博徳, "スタティックスケジューリングを用いた電子回路シミュレーションの粗粒度/近細粒度階層型並列処理手法", 情報処理学会論文誌, Vol.37, No.10, Oct. 1996.
  146. A.Yoshida, H. Kasahara, "Data Localization Using Loop Aligned Decomposition for Macro-Dataflow Processing", Proc. of 9th Workshop on Languages and Compilers for Parallel Computers, pp.56-74, Aug. 1996.
  147. 中野 恵一, 笠原 博徳, "ソーテッドコードブックベクトル量子化の並列処理", 情報処理学会論文誌, Vol.37, No.7, Jul. 1996.
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  149. Akimasa Yoshida, Kenichi Koshizuka, Hironori Kasahara , "Data-Localization for Fortran Macro-Dataflow Computation Using Partial Static Task Assignment", Proc. of 10th ACM International Conference on Supercomputing, pp.61-68, May. 1996.
    150. 1995
  150. 吉田 明正, 前田 誠司, 尾形 航, 笠原 博徳, "Fortranマルチグレイン並列処理におけるデータローカライゼーション手法", 情報処理学会論文誌, Vol. 36, No. 7, pp.1551-1559, Jul. 1995.
  151. 合田 憲人, 岩崎 清, 岡本 雅巳, 笠原 博徳, 成田 誠之助, "共有メモリ型マルチプロセッサシステム上でのFortran粗粒度タスク並列処理の性能評価", 情報処理学会論文誌, Vol. 37, No. 3, pp.418-429, Mar. 1996.
  152. K. Aida, K. Iwasaki, H. Kasahara and S. Narita, "Performance Evaluation of Macro-Dataflow Computation on Shared Memory Multiprocessor", Proc. IEEE Pacific Rim Conference on Communications, Computers, and Signal Processing, pp.50-54, May. 1995.
  153. M. Okamoto, K. Yamashita, H. Kasahara and S. Narita, "Hierarchical Macro-Dataflow Computation Scheme", Proc. IEEE Pacific Rim Conference on Communications, Computers, and Signal Processing, pp.44-49, May. 1995.
  154. W. Ogata, K. Fujimoto, M. Oota and H. Kasahara, "Compilation Scheme for Near Fine Grain Parallel Processing on a Multiprocessor System without　Explicit Synchronization", Proc. IEEE Pacific Rim Conference on Communications, Computers, and Signal Processing, pp.327-332, May. 1995.
  155. Y. Maekawa, K. Nakano, M. Takai and H. Kasahara, "Near Fine Grain Parallel Processing of Circuit Simulation Using Direct Method", Proc. IEEE Pacific Rim Conference on Communications, Computers, and Signal Processing, pp.272-276, May. 1995.
  156. A.Yoshida, S. Maeda, K. Fujimoto and H. Kasahara, "A Data-Localization Scheme Using Task-Fusion for Macro-Dataflow Computation", Proc. IEEE Pacific Rim Conference on Communications, Computers, and Signal Processing, pp.135-141, May. 1995.
  157. A.Yoshida, S. Maeda, K. Fujimoto and H. Kasahara, "Data-Localization for Macro-Dataflow Computation Using Static Macrotask Fusion", Proc. Fifth Workshop on Compilers for Parallel Computers, pp.440-453, Jul. 1995.
    158. 1994
  158. 岡本 雅巳, 合田 憲人, 宮沢 稔, 本多 弘樹, 笠原 博徳, "OSCARマルチグレインコンパイラにおける階層型マクロデータフロー処理手法", 情報処理学会論文誌, Vol. 35, No. 4, pp.513-521, Apr. 1994.
  159. 尾形 航, 吉田 明正, 合田 憲人, 岡本 雅巳, 笠原 博徳, "スタティックスケジューリングを用いたマルチプロセッサシステム上の無同期近細粒度並列処理", 情報処理学会論文誌, Vol. 35, No. 4, pp.522-531, Apr. 1994.
  160. 前川 仁孝, 田村 光雄, 中山 功, 吉成 泰彦, 笠原 博徳, "直接法を用いた電子回路シミュレーションの近細粒度並列処理", 電気学会論文誌C, Vol. 114-C, No. 5, pp.579-587, May. 1994.
  161. 吉田 明正, 前田 誠司, 尾形 航, 笠原 博徳, "Fortranマクロデータフロー処理におけるデータローカライゼーション手法", 情報処理学会論文誌, Vol. 35, No. 9, pp.1848-1860, Sep. 1994
  162. 中野 恵一, 笠原 博徳, "ソートされたコードブックを用いた高速ベクトル量子化", 電子情報通信学会論文誌, Vol. J77-D-II, No. 11, pp.1984-1992, Oct. 1994.
  163. 吉田 明正, 前田 誠司, 尾形 航, 笠原 博徳, "Fortran粗粒度並列処理におけるDoall/シーケンシャルループ間データローカライゼーション手法", 電子情報通信学会論文誌, Vol. J78-D-I, No. 2, Feb. 1995.
    164. 1993
  164. 笠原博徳, "並列処理のためのシステムソフトウェア", 情報処理, Vol. 34, No. 9, Sep. 1993
  165. 中野恵一, 笠原博徳, "マルチプロセッサシステム上での非線形方程式求解の並列処理", 電気学会論文誌, Vol. 113-C, No. 11, Nov. 1993.
  166. 山本裕治, 鳥居宏行, 前川仁孝, 田村光雄, 笠原博徳, 成田誠之助, "連続・離散時間制御システムシミュレーションの並列処理", 電気学会論文誌C, Vol. 113-C, No. 11, Nov. 1993.
  167. 笠原博徳, "並列処理ソフトウェア", 電気学会論文誌C, Vol. 113-C, No. 11, Nov. 1993.
  168. H. Honda, K. Aida, M. Okamoto, A. Yoshida, W. Ogata, H. Kasahara, "Fortran Macro-Dataflow Compiler", Proceedings of Fourth Workshop on Compilers for Parallel Computers, Dec. 1993.
    169. 1992
  169. H. Kasahara, A. Itoh, H. Tanaka, K. Itoh, "A Parallel Optimization Algorithm for Minimum Execution-Time Multiprocessor Scheduling Problem", Systems and Computers in Japan, Vol. 23, No. 13, 1992.
  170. 笠原 博徳, ウィチェン プレムチャイサワディ, 田村 光雄, 前川 仁孝, 成田 誠之助, "OSCAR上でのスパース行列直接解法の並列処理", 情報処理学会論文誌, Vol. 33, No. 4, Apr. 1992.
  171. W. Premchaiswadi, Y. Maekawa, M. Tamura, H. Kasahara, S. Narita, "A Parallel Processing Scheme of Circuit Simulation on a Mulitprocessor System", 日本シミュレーション学会論文誌, Vol. 11, No. 2, Jun. 1992.
  172. 笠原 博徳, "リアルタイムシステムにおける並列処理", 計測と制御, Vol. 31, No. 7, Jul. 1992.
  173. 笠原 博徳, 合田 憲人, 吉田 明正, 岡本 雅巳, 本多 弘樹, "Fortranマクロデータフロー処理のマクロタスク生成手法", 電子情報通信学会論文誌, Vol. J75-D-I, No. 8, pp.511-525, Aug. 1992.
  174. 藤原 和典, 白鳥 健介, 鈴木 真, 笠原 博徳, "データプレロードおよびポストストアを考慮したマルチプロセッサスケジューリングアルゴリズム", 電子情報通信学会論文誌, Vol. J75-D-I, No. 8, pp.495-503, Aug. 1992.
  175. 本多 弘樹, 合田 憲人, 岡本 雅巳, 笠原 博徳, "Fortranプログラム粗粒度タスクのOSCARにおける並列実行方式", 電子情報通信学会論文誌, Vol. J75-D-I, No. 8, pp.526-535, Aug. 1992.
  176. 甲斐 宗徳, 加茂 正充, 佐藤 弘幸, 笠原 博徳, "密結合型マルチプロセッサシステム上でのProlog OR並列処理の実現", 電子情報通信学会論文誌, Vol. J75-D-I, No. 8, pp.675-684, Aug. 1992.
  177. H. Kasahara, H. Honda, K. Aida, M. Okamoto, A. Yoshida, W. Ogata, S. Narita, "Near Fine Grain Parallelizing Compiler for OSCAR", Proceedings of Third Workshop on Compilers for Parallel Computers, Jul. 1992.
    178. 1991
  178. W.Pemchaiswadi ,H. Kasahara, S. Narita, "マルチプロセッサシステム上での非線形微分方程式の並列処理", シミュレーション, Vol. 10, No. 2, pp.140-150, Jun. 1991.
  179. H. Kasahara, H. Honda, S. Narita, "A FORTRAN Parallelizing Compilation Scheme for OSCAR Using Dependence Graph Analysis", Trans. of IEICE, Vol. E74, No. 10, pp.3105-3114, Oct. 1991.
  180. 笠原 博徳, 伊藤 敦, 田中 久充, 伊藤 敬介, "実行時間最小マルチプロセッサスケジューリング問題に対する並列最適化アルゴリズム", 電子情報通信学会論文誌, Vol. J74-D-I, No. 11, pp.755-764, Nov. 1991.
  181. H. Honda, A. Mogi, A. Ogura, H. Kasahara, S. Narita, "Parallel Processing Scheme for a FORTRAN Program on a Multiprocessor System OSCAR", IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, Vol. 1, pp.9-12, May. 1991.
  182. M. Kai, H. Kasahara, "An Efficient OR-Parallel-Processing Scheme of PROLOG : Hierarchical Pincers Attack Search", Proc. of IEEE Pacific Rim Conf. on Communication, Computer and Signal Processing, Vol. 2, pp.677-680, May. 1991.
  183. H. Kasahara, H. Honda, A. Mogi, A. Ogura, K. Fujiwara, S. Narita, "A Multi-grain Parallelizing Compilation Scheme for OSCAR (Optimally Scheduled Advanced Multiprocessor)", Fourth International Workshop on Languages and Compilers for Parallel Computing, pp.283-297, Aug. 1991.
  184. H. Kasahara, W. Premchaiswadi, M. Tamura, Y. Maekawa, S. Narita, "Parallel Processing of Sparse Matrix Solution Using Fine Grain Tasks on OSCAR (Optimally Scheduled Advanced Multiprocessor)", International Conference on Parallel Processing, pp.322-323, Aug. 1991.
  185. H. Kasahara, H. Honda, K. Aida, M. Okamoto, S. Narita, "OSCAR FORTRAN Compiler", International Logic Programming Symposium, Workshop on Compilation of (Symbolic) Languages for Parallel Computers, Nov. 1991.
    186. 1990
  186. 本多 弘樹, 水野 聡, 笠原 博徳, 成田 誠之助, "OSCAR上でのFortranプログラム基本ブロックの並列処理手法", 電子情報通信学会論文誌, Vol. J73-D-I, No. 9, pp.756-766, Sep. 1990.
  187. 佐々木 和則, 神余 浩夫, 笠原 博徳, 成田 誠之助, "原子プラント状態予測シミュレータへの並列処理の適用", 日本原子力学会誌, Vol. 32, No. 10, pp.1009-1022, Oct. 1990.
  188. 本多 弘樹, 岩田 雅彦, 笠原 博徳, "Fortranプログラム粗粒度タスク間の並列性検出手法", 電子情報通信学会論文誌, Vol. J73-D-I, No. 1, pp.951-960, Dec. 1990.
  189. H. Kasahara, H. Honda, M. Iwata, M. Hirota, "A Compilation Scheme for Macro-dataflow computation on Hierarchical Multiprocessor System", Proc.Int Conf. on Parallel Processing, pp.294-295, 1990.
  190. H. Kasahara, H. Honda, S. Narita, "Parallel Processing of Near Fine Grain Tasks Using Static Scheduling on OSCAR (Optimally Scheduled Advanced Multiprocessor)", Proceedings of IEEE Supercomputing '90, pp.856-864, Nov. 1990.
    191. 1989
  191. 笠原 博徳, "並列処理技術-マルチプロセッサシステムのハードウェア", 日本シミュレーション学会誌, Vol. 8, No. 2, Jun. 1989.
  192. 笠原 博徳, "並列処理技術-並列処理におけるソフトウェア", 日本シミュレーション学会誌, Vol. 8, No. 3, Sep. 1989.
  193. 笠原 博徳, "並列処理技術-マルチプロセッサシステム上での並列シュミレーションの実例", 日本シミュレーション学会誌, Vol. 8, No. 4, Dec. 1989.
  194. H. Kasahara, "Parallel Processing of Robot Arm Dynamic Control Computation on Multimicroprocessors", Microprocessors and Microsystems, Vol. 14, No. 1, pp.3-9, Jan. 1990.
  195. 笠原 博徳, "最適化並列コンパイラ技術の現状", 電子情報通信学会学会誌, Vol. 73, No. 3, Mar. 1990.
  196. H. Kasahara, S. Narita, "Parallel Processing of Robot Control and Simulation", Proc. Workshop on Parallel Algorithm of IEEE Conf. on Robotics and Automation, May. 1989.
  197. H. Kasahara, H. Honda, S. Narita, "Parallel Processing of Real-time Dynamic Systems Simulation on OSCAR (Optimally SCheduled Advanced multiprocessoR)", Proc. 3rd NASA NSF DOD Conf. on Aerospace Computational Control, Aug. 1989.
    198. 1988
  198. H. Kasahara, M. Kai, S. Narita, H. Wada, "Application of DF/IHS for Minimum Total Weighted Flow Time Multiprocessor Scheduling Problems", Systems and Computers in Japan, Vol. 19, No. 6, pp.25-34, Jun. 1988.
  199. 甲斐宗徳, 小林和男, 笠原博徳, "階層型挟み打ち探索によるPROLOG OR並列処理手法", 情報処理学会論文誌, Vol. 29, No. 7, Jul. 1988.
  200. 笠原博徳, 成田誠之助, "ロボット用高度並列コンピュータの展望", 日本ロボット学会誌, Vol. 6, No. 4, Aug. 1988.
  201. 笠原博徳, 成田誠之助, 橋本親, "OSCAR(Optimally Scheduled Advanced Multiprocessor)のアーキテクチャ", 電子情報通信学会論文誌, Vol. J71-D, No. 8, Aug. 1988.
  202. 笠原博徳, 高根栄二, 佐藤東哉, 久永裕嗣, 成田誠之助, "汎用目的マルチプロセッサ・システムOSCAR上での常微分方程式求解の並列処理", 早稲田大学情報科学研究教育センタ紀要, Vol. 8, Autumn, Sep. 1988.
  203. H. Kasahara, M. Iwata, S. Narita, H. Fujii, "Parallel Processing of Robot Dynamics Simulation Using Optimal Multiprocessor Scheduling Algorithms", Systems and Computers in Japan, Vol. 19, No. 10, pp.45-54, Oct. 1988.
  204. 笠原博徳, "並列処理技術-並列処理の概要-", 日本シミュレーション学会誌, Mar. 1989.
  205. H. Kasahara, H. Honda, E. Takane, S. Narita, "A Parallel Processing Scheme for the Solution of Ordinary Differential Equations Using Static Optimal Multiprocessor Scheduling Algorithms", PROCEEDINGS OF THE THIRD ANNUAL PARALLEL PROCESSING SYMPOSIUM, Mar. 1989.
  206. H. Kasahara, H. Nakayama, E. Takane, S. Narita, "Parallel Processing for the Solution of Sparse Linear Equations on OSCAR (Optimally Scheduled　Advanced Multiprocessor)", Proc. IEE BISL CONPAR 88(Cambridge Univ Press), Sep. 1988.
    207. 1987
  207. 笠原 博徳, 和田 英彦, 甲斐 宗徳, 成田 誠之助, "トータル加重フロー時間最小マルチプロセッサスケジューリング問題に対するDF/IHSの応用", 電子情報通信学会論文誌, Vol. J70-D, No. 6, pp.1083-1091, Jun. 1987.
  208. 伊東 俊哉, 中野 恵一, 笠原 博徳, 成田 誠之助, "オプティカル・フロー計算およびカメラの運動パラメータ決定のための並列処理手法", 早稲田大学情報科学研究教育センタ紀要, Vol. BCIW'87-A-5, pp.47-59, May. 1987.
  209. 笠原 博徳, 成田 誠之助, "並列処理技術", コンピュートロール(コロナ社), Vol. 19, pp.6-13, Jul. 1987.
  210. 笠原博徳, "ロボット制御における並列処理", コンピュートロール(コロナ社), Vol. 19, pp.97-103, Jul. 1987.
  211. 笠原 博徳, 藤井 博文, 岩田 雅彦, 成田 誠之助, "最適マルチプロセッサスケジューリングアルゴリズムを用いたロボットダイナミックスシミュレーションの並列処理", 電子情報通信学会論文誌, Vol. J70-D, No. 9, pp.1783-1790, Sep. 1987.
  212. 笠原 博徳, 藤井 稔久, 本多 弘樹, 成田 誠之助, "スタティック・マルチプロセッサ・スケジューリング・アルゴリズムを用いた常微分方程式求解の並列処理", 情報処理学会論文誌, Vol. 28, No. 10, pp.1060-1070, Oct. 1987.
  213. 笠原 博徳, "マルチプロセッサスケジューリング問題に対する分枝限定法の適用", 日本オペレーションリサーチ学会誌, Vol.33, No.1, Jan. 1988., http://www.orsj.or.jp/~archive/menu/03_33.html
  214. 笠原博徳, "マルチプロセッサ・システムの研究動向", 電気学会論文誌C分冊, Vol. 108-C, No. 2, Feb. 1988.
  215. H. Kasahara, T. Fujii, H. Nakayama, S. Narita, Leon O.Chua, "A Parallel Processing Scheme for the Solution of Sparse Linear Equations Using Static Optimal Multiprocessor Scheduling Algorithms", Proc. 2nd Int. Conf. on Supercomputing, May. 1987.
  216. H. Kasahara, H. Fujii, M. Iwata, "Parallel Processing of Robot Motion Simulation", Proc. IFAC 10th World Congress, pp.329-336, Jul. 1987.
    217. 1986
  217. 甲斐 宗徳, 笠原 博徳, 成田 誠之助, 宇梶 仁志, "マルチプロセッサ・リアルタイム制御システムにおけるタスクスケジューリング手法", 電気学会論文誌C分冊, Vol. 106-C, No. 12, Dec. 1986.
  218. 甲斐 宗徳, 笠原 博徳, 成田 誠之助, 本位田 真一, 田村 信介, "マルチプロセッサスケジューリング・アルゴリズムを用いた論理型オブジェクト指向言語MENDELの並列処理手法", 電気学会論文誌C分冊, Vol. 107-C, No. 2, Feb. 1987.
  219. H. Kasahara, H. Fujii, M. Iwata, H. Honda, S. Narita, "Real-time simulation of robot motion dynamics on a multiprocessor", Proceedings of the Seventh IFAC Workshop on Distributed Computer Control Systems 1986, Oct. 1986.
  220. H. Kasahara, H. Fujii, M. Iwata, H. Honda, S. Narita, "A Multi processor Robot Motion Simulator", Proc. JSST International Conference, Jul. 1986.
    221. 1985
  221. M. Kai, A. Ito, H. Wada, H. Kasahara, S. Narita, H. Ukaji, "Dynamic Task Scheduling for Control of Hot Strip Mill Lines", BUlletin of Centre for Informatics, Waseda University, Vol. 2, Autumn, 1985.
  222. H. Kasahara, S. Narita, "Parallel Processing of Robot Arm Control Computation on a Multimicroprocessor System", IEEE Journal of Robotics and Automation, Vol. RA-1, No. 2, Jun. 1985.
  223. M. Kai, H. Wada, H. Kasahara, S. Narita, H. Ukaji, "Load Distribution Among Real time Control Computers: Multiprocessor Control of Tandem Rolling Mills", Proc. of 6th IFAC Workshop on DCCS, May. 1985.
  224. H. Kasahara, H. Honda, M. Kai, T. Seki, S. Narita, "Parallel Processing for Simulation of Dynamical Systems", Proc. of IFAC 7th Conf. on Digital Computer Application to Process Control System, Sep. 1985.
  225. H. Kasahara, S. Narita, "An Approach to Supercomputing Using Multiprocessor Scheduling Algorithms", Proc. of IEEE 1st International Conf. on Supercomputing, Dec. 1985.
    226. 1984
  226. 笠原博徳, 成田誠之助, "マルチプロセッサ・スケジューリング問題に対する実用的な最適及び近似アルゴリズム", 電子通信学会論文誌D, Vol. 67-D, No. 7, Jul. 1984.
  227. 笠原博徳, 成田誠之助, "マルチプロセッサ・スケジューリング・アルゴリズムを用いたロボット制御計算の並列処理手法", 日本ロボット学会誌, Vol. 2, No. 5, Oct. 1984.
  228. H. Kasahara, S. Narita, "Practical Multiprocessor Scheduling Algorithms for Efficient Parallel Processing", IEEE Trans. on Computers, Vol. C-33, No. 11, pp.1023-1029, Nov. 1984.
  229. H. Kasahara, S. Narita, "Practical Multiprocessor Scheduling Algorithms for Efficient Parallel Processing", Systems and Computers in Japan, Vol. 16, No. 2, Mar. 1985.
  230. H. Kasahara, S. Narita, "Load Distribution among Real-time Control Computers Connected via Communication Media", Proc. of 9th IFAC World Congress, Jul. 1984.
  231. H. Kasahara, S. Narita, "Integrated Simulation System for Design and Evaluation of Distributed Computer Control Systems", Proc. of 9th IFAC World Congress, Jul. 1984.
    232. 1983
  232. 笠原博徳, 成田誠之助, "マルチプロセッサ連続システムシミュレーションのための並列処理手法", 日本シミュレーション学会誌, Vol. 2, No. 3, Nov. 1983.
    233. 1982
  233. H. Kasahara, S. Narita, "Parallel Processing for Real Time Control and Simulation of Distributed Computer Control Systems", Proc. of 4th IFAC　Workshop on DCCS, May. 1982.
    234. 1981
  234. S. Narita, H. Tachiyeda, K. Omata, T. Mimura, H. Kasahara, "A Parallel Processing Algorithm for Fast Load-Flow and Stability Calculations", Proc. of　the Seventh Power Systems Computation Conference, Jul. 1981.


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