1994

Journal

  1. M. Okamoto, K. Aida, M. Miyazawa, H. Honda, H. Kasahara, ``A Hierarchical Macro-dataflow Computation Scheme of OSCAR Multi-grain Compiler'', Trans. of IPSJ, Vol.35, No.4, pp.513-521, Apr.1994.
  2. W. Ogata, A. Yoshida, K. Aida, M. Okamoto, H. Kasahara, ``Near Fine Grain Parallel Processing without Synchronization using Static Scheduling'', Trans. of IPSJ, Vol.35, No.4, pp.522-531, Apr.1994.
  3. Y. Maekawa, M. Tamura, I. Nakayama, Y. Yoshinari, H. Kasahara, ``Near Fine Grain Parallel Processing of Circuit Simulation Using Direct Method'', Trans. IEE of Japan, Vol.114-C, No.5, pp.579-587, May.1994.
  4. A. Yoshida, S. Maeda, W. Ogata, H. Kasahara, ``A Data-Localization Scheme for Fortran Macro-Dataflow Computation'', Trans. of IPSJ, Vol.35, No.9, pp.1848-1860, Sep.1994.
  5. K. Nakano, H. Kasahara, ``Fast Vector Quantization Using Sorted Codebook'', Trans. of IEICE, Vol.J77-D-II, NO.10, pp.1984-1992, Oct.1994.
  6. A. Yoshida, S. Maeda, W. Ogata, H. Kasahara, ``A Data-Localization Scheme among Doall/Sequential Loops for Fortran Coarse-Grain Parallel Processing'', Trans. of IEICE, Vol.J78-D-I, No.2, Feb.1995.

Symposium with Review

  1. A. Yoshida, S. Maeda, W. Ogata, H. Kasahara, ``A Data-Localization Scheme for Multi-Grain Parallel Processing'', Joint Symposium on Parallel Processing 1994, May.1994.

Technical Report

  1. A. Yoshida, S. Maeda, W. Ogata, H. Kasahara, ``A Data-Localization Scheme among Doall/Sequential Loops for Macro-Dataflow Computation'', Technical Report of IEE Japan, IP-94-40, Dec.1994.
  2. W. Ogata, M. Oota, A. Yoshida, M. Okamoto, H. Kasahara, ``Compilation Scheme for Near Fine Grain Parallel Processing without Synchronization on Multiprocessor System OSCAR'', SIG Notes of IEE, IP-94-41, Dec.1994.
  3. Y. Maekawa, M. Takai, T. Itoh, T. Nishikawa, H. Kasahara, ``Parallel Processing Scheme of Electronic Circuit Simulation Using Circuit Tearing'', SIG Notes of IEE, IP-94-44, Dec.1994.
  4. K. Aida, M. Okamoto, H. Kasahara, S. Narita, ``A Multi-job Execution Scheme for Macro-dataflow Computation'', SIG Notes of IPSJ, OS-65-4, Jul.1994.
  5. K. Nakano, H. Kasahara, ``Parallel Search Scheme for Fast Vector Quantization with Sorted Codebook'', Technical Report of IEICE, CPSY94-42, Jul.1994.
  6. K. Aida, M. Okamoto, H. Kasahara, S. Narita, ``Scheduling Scheme among Hierarchically Parallel Executed Jobs'', SIG Notes of IPSJ, ARC-111-1, Mar.1995.

Annual Convention

  1. A. Yoshida, S. Maeda, W. Ogata, K. Yamashita, H. Kasahara, ``A Data-Localization Scheme among Doall and Sequential Loops for Coarse-Grain Parallel Processing`` Proc. 49th Annual Convention IPSJ, 4T-7, Sep.1994.
  2. K. Yamashita, Y. Yasuda, M. Miyazawa, H. Kasahara, ``A data dependence analysis scheme using array subscript bit vector'', Proc. 50th Annual Convention IPSJ, 1J-2, Mar.1995.
  3. W. Ogata, M. Oota, A. Yoshida, M. Okamoto, H. Kasahara, ``Parallelizing Code Scheduling on Near-Fine Grain Parallel Processing without Synchronization'', Proc. 50th Annual Convention IPSJ, 1J-3, Mar.1995.
  4. A. Yoshida, W. Ogata, M. Okamoto, K. Aida, H. Kasahara, ``A Near-Fine-Grain Task Scheduling Scheme for Data-Localization on Multi-Grain Parallel Processing'', Proc. 50th Annual Convention IPSJ, 1J-5, Mar.1995.
  5. K. Fujimoto, H. Kasahara, ``Data Transfer Overhead Hiding by Data Preloading and Poststoring in Automatic Parallelizing Compiler'', Proc. 50th Annual Convention IPSJ, 1J-7, Mar.1995.
  6. K. Iwasaki, K. Aida, H. Kasahara, S. Narita, ``Performance Evaluation of Macro-dataflow Computation on Shared-memory Multi Processor System'', Proc. 50th Annual Convention IPSJ, 1B-8, Mar.1995.
  7. T. Itoh, Y. Maekawa, M. Takai, K. Nishikawa, H. Kasahara, ``Hierarchal Parallel Processing of Electronic Circuit Simulation with Coarse and Near Fine Grain Tasks'', Proc. 50th Annual Convention IPSJ, 2J-9, Mar.1995.
  8. K. Serizawa, Y. Maekawa, K. Nakano, H. Kasahara, ``Parallel Processing of Recurrent Neural Network Simulation'', Proc. 1995 Spring Annual Convention IEICE Mar.1995.
  9. M. Oota, W. Ogata, H. Kasahara, ``A Multiprocessor Architecture Simulator for Multi-Grain Parallel Processing'', Proc. 1995 Spring Annual Convention IEICE Mar.1995.