2011

Papers

1. Akihiro Hayashi, Mamoru Shimaoka, Hiroki Mikami, Masayoshi Mase, Yasutaka Wada, Jun Shirako, Keiji Kimura, and Hironori Kasahara, "OSCAR Parallelizing Compiler and API for Real-time Low Power Heterogeneous Multicores", 16th Workshop on Compilers for Parallel Computing(CPC2012), Padova, Italy, Jan. 2012. (To appear)
2. Akihiro Hayashi, Yasutaka Wada, Takeshi Watanabe, Takeshi Sekiguchi, Masayoshi Mase, Jun Shirako, Keiji Kimura and Hironori Kasahara, "Parallelizing Compiler Framework and API for Heterogeneous Multicores", IPSJ Transactions on Advanced Computing Systems, Vol.5, No.1, pp.68-79,Nov. 2011.
3. Yasutaka Wada, Akihiro Hayashi, Takeshi Masuura, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, and Hironori Kasahara, "A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture", Transactions on High-Performance Embedded Architectures and Compilers IV,Lecture Note in Computer Science, Springer, Vol. 6760, pp.215-233, Nov. 2011.
4. Sameh Samra, Ahmed El-Mahdy, Walid Gomaa, Yasutaka Wada, Amin Shoukry, "Efficient Parallel Implementations of Controlled Optimization of Traffic Phases", Proc. of The 11th International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP 2011), Oct. 2011.
5. Hiroki Mikami, Shumpei Kitaki, Masayoshi Mase, Akihiro Hayashi, Mamoru Shimaoka, Keiji Kimura, Masato Edahiro, and Hironori Kasahara, "Evaluation of Power Consumption at Execution of Multiple Automatically Parallelized and Power Controlled Media Applications on the RP2 Low-power Multicore", Proc. of LCPC 2011(The 24th International Workshop on Languages and Compilers for Parallel Computing ) , Colorado State University, Fort Collins, Colorado, Sept 8-10, 2011.
6. Osamu NISHII, Yoichi YUYAMA, Masayuki ITO, Yoshikazu KIYOSHIGE,YusukeNITTA, Makoto ISHIKAWA, Tetsuya YAMADA, Junichi MIYAKOSHI,YasutakaWADA, Keiji KIMURA, Hironori KASAHARA, and Hideo MAEJIMA,"A 45-nm37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 BitInstruction-SetGeneral-Purpose Core",IEICE TRANSACTIONS on Electronics, Vol. E94-C, No. 4,pp.663-669, Apr. 2011.

Invited Talks

1. Hironori Kasahara, "Automatic Parallelizing and Power Control Compiler and API for Manycore Processors", NEDO Manycore Symposium, Tokyo, Japan, Mar. 30. 2012.
2. Hironori Kasahara, "Multicore Technology for Green Computing", The Japan Society of Applied Physics (JSAP) the 59th Spring Meeting Special Symposium, Waseda University, Tokyo, Japan, Mar. 15. 2012.
3. Hironori Kasahara, "Multicore/Manycore Architectures and Software for Green Computing", The 34th Electrical Engineering Conference(EECON-34), Pattaya, Thai, Dec. 01. 2011.
4. Hironori Kasahara, "Low Power Multicores, Parallelizing Compiler and Multiplatform API for Green Computing", Dasan Conference on "Green IT", The Korean Federation of Science and Technology Society, Jeju, Korea , Nov. 03. 2011.
5. Hironori Kasahara, "Green Computing Systems Reserch and Development Center", Innovation Policy Social Meeting in October, Tokyo, Japan, Oct. 21. 2011.
6. Hironori Kasahara, "Homogeneous and Heterogeneous Multicore / Manycore Processors, Parallelizing Compiler and Multiplatform API for Green Computing", Keynote Speech, MPSoC2011(11th International Forum on Embedded MPSoC and Multicore), July 7, 2011, Beaune, France
7. Hironori Kasahara, "Low Power Real-time Homogeneous &Heterogeneous Multicores, Automatic Parallelizing Compilersand Multi-Platoform API",Sig. on The 5th Automoble Control and Model,The Society of Automotive Engineers of Japan (JSAE)　＆The Society of Instrument and Control Engineers （SICE),June 8, 2011.
8. Hironori Kasahara, "Future of Green Computing", Waseda Univ. Green Computing Systems Research & Development Center Opening Memorial Symposium:Green Computing for Opening Future --For future of enviroment friendly computing--, May. 13, 2011.

Technical Reports

1. Yoichi Abe, Ryo Ishizuka, Ryota Daigo, Gakuho Taguchi, Keiji Kimura, Hironori Kasahara, "An Examination of Accelerating Many-core Architecture Simulation for Parallelized Media Applications", Technical Report of IPSJ, Vol. 2012-ARC-199, No. 3, Mar. 2012.
2. Keiichi Tabata, Keiji Kimura, Hironori Kasahara, "Inlining Analysis of Exception Flow and Fast Method Dispatch on Automatic Parallelization of Java", Technical Report of IPSJ, Vol. 2012-ARC-199, No. 9, Mar. 2012.
3. Keiji Kimura, Masayoshi Mase, Hironori Kasahara, "A Definition of Parallelizable C by JISX0180:2011 "Framework of establishing coding guidelines for embedded system development", ETNET2012, Mar. 2012.
4. Akihiro Hayashi, Takuji Matsumoto, Hiroki Mikami, Keiji Kimura, Keiji Yamamoto, Hironori Saki, Yasuyuki Takatani and Hironori Kasahara, "Automatic Parallelization of Dose Calculation Engine for A Particle Therapy on SMP Servers", Technical Report of IPSJ, Vol.2011-ARC189HPC132-2, Nov. 2011.
5. Ryo Ishizuka, Youichi Abe, Ryota Daigo, Keiji Kimura and Hironori Kasahara, "An Evaluation of An Acceleration Technique of Many Core Architecture Simulator Considering Science Technology Calculation Program Structure", Technical Report of IPSJ, Vol2011-HPC-130-16, July.2011.
6. Yuki Taira, Keiji Kimura and Hironori Kasahara, "Examination of Parallelization by CUDA in SPEC benchmark program", Technical Report of IPSJ, Vol.2011-HPC-130-16, Jul.2011.
7. Akihiro Hayashi, Takeshi Sekiguchi, Masayoshi Mase, Yasutaka Wada, Keiji Kimura and Hironori Kasahara, "Hiding I/O overheads with Parallelizing Compiler for Media Applications", Techinical Report of IPSJ, Vol.2011-ARC-195OS117-14, Apr. 2011.

Symposiums

1. Akihiro Hayashi, Takuji Matsumoto, Hiroki Mikami, Keiji Kimura, Keiji Yamamoto, Hironori Saki, Yasuyuki Takatani and Hironori Kasahara, "Automatic Parallelization of Dose Calculation Engine for A Particle Therapy", Symposium on High-Performance Computing and Computer Science(HPCS2012), Jan. 2012. (With Review)

Media

Patents

　Registration of patent

1. "MEHTOD FOR CONTROLLING HETEROGENEOUS MULTIPROCESSOR AND MULTIGRAIN PARALLELIZING COMPILER", 4936517(JP Patent), Mar.02.2012.
2. "MULTIPROCESSOR SYSTEM AND METHOD OF SYNCHRONIZATION FOR MULTIPROCESSOR SYSTEM", 8108660(US Patent), Jan.31.2012.
3. "LOCAL MEMORY MANAGEMENT, INFORMATION-PROCESSING DEVICE, PROGRAM CREATION METHOD AND PROGRAM", 2459802(GB Patent), Jan.04.2012.
4. "LOCAL MEMORY MANAGEMENT, INFORMATION-PROCESSING DEVICE, PROGRAM CREATION METHOD AND PROGRAM", 2478874(GB Patent), Dec.28.2011.
5. "GLOBAL COMPILER FOR CONTROLLING HETEROGENEOUS MULTIPROCESSOR", 8051412(US Patent), Nov.01.2011.
6. "MULTIPROCESSOR", 4784792(JP Patent), Jul.22.2011.
7. "GLOBAL COMPILER FOR CONTROLLING HETEROGENEOUS MULTIPROCESSOR", 4784827(JP Patent), Jul.22.2011.
8. "MULTIPROCESSOR AND MULTIPROCESSOR SYSTEM", 4784842(JP Patent), Jul.22.2011.

　Published applications for patent

1. "LOCAL MEMORY MANAGEMENT, INFORMATION-PROCESSING DEVICE, PROGRAM CREATION METHOD AND PROGRAM", 2478874(GB Publication), Sep.21.2011. [Registration of patent:2478874(GB Patent), Dec.28.2011.]
2. "METHOD OF GENERATING CODE WHICH IS EXECUTABLE BY A PROCESSOR, STORAGE AREA MANAGEMENT METHOD , AND STORAGE MEDIUM WHICH STORES A CODE CODE GENERATION PROGRAM", 2011-128803(JP Publication), Jun.30.2011. [Registration of patent:5283128(JP Patent), Jun.07.2013.]
3. "METHOD OF GENERATING CODE EXECUTABLE BY PROCESSOR", 11/74569(WO Publication), Jun.23.2011.

Awards

1. Hiroki Mikami, "IPSJ Computer Architecture Young Presentation Award", Apr. 2011.

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